EE 216 數位系統導論
Introduction to Digital Systems
蘇朝琴 Chauchin Su
國立中央大學電機工程學系
Depart of Electrical Engineering, National Central University
Chung-Li, Taiwan 32054, R.O.C.

學期總成績公佈於此：考試成績 ，若有問題請儘速找我。

課目名稱：數位系統導論  Introduction to Digital Systems
課程編號：EE 216  〈電機一年級 B 班〉
授課時間：八十九學年度第二學期 〈周一 3,4  周三 2 〉教室：EI121
授課老師：蘇朝琴 (EI-403, X4465, ccsu@ee.ncu.edu.tw)
修課學生：大一  (電一B) 三學分  必修
課程簡介： (內含上課投影片 MicroSoft PowerPoint Files

本課程為數位電路設計的基本課程，其配合之實驗課程為電工實驗一。

本課程的後續的相關課程包括計算機組織，超大型積體電路導論，以及超大型積體電路所有相關科目。理論課程的後續則以離散數學為主。

課程內容如以下所列，實驗內容則包含一半的 TTL電路實驗，另一半則為 FPGA 電路實驗。

• Preface
• Chapter 1:  Numbers and codes in digital systems
• Chapter 2:  Boolean algebraic methods for digital design
• Chapter 3:  Logic function simplification
• Chapter 4:  Combinational building blocks
• Chapter 5:  Programmable logic devices
• Chapter 6:  Sequential circuits
• Chapter 7:  Synchronous sequential circuit design
• Chapter 8:  Sequential circuit simplification

教科書：

• V.P. Nelson, H.T. Nagle, B.D. Carroll, and J.D. Irwin, Digital Logic Circuit Analysis and Design, Prentice Hall, 1995.
• D.D. Gajski, Principles of Digital Design, Prentice Hall, 1997. (參考用)

評分標準：

• 小考      30% (8~10次)
• 期中考  30%
• 期末考  40%

助教：麥世達  EI-358 (359,360) Tel: 4576

感謝：

本課程的成功首先要感謝教育部顧問室自八十二學年度以來，每年持續的電腦與超大型積體電路教育改進計劃，再來則要感謝國科會工程處晶片中心提供完善的電路設計軟體。系上持續的硬體設備的更新也是功不可沒。

小考：

1. 3/5：Decimal to Binary Translation, Binary Add/Subtraction Operation, Overflow Detection
2. 3/12：Proof of  Demogan's  Theory, Example 2.20, Problem 2.1, Proof of Consensus
3. 3/19 : f(a,b,c)=m0+m2+m3+m7, (1) write the Canonical PoS form, (2) reduce the function to a minimal SoP, (3) reduce the function into a minimal PoS, (4) use NAND to implement the circuits. 在考試時，仍然維持三個變數，作相同的動作。參考資料在講義 P.25 for (1), (2), (3)，P49 for (4)。
4. 3/26: f(a,b,c,d) = m0+m1+m2+m4+m6+m8+m11+m12, (1) write the K-Map, (2) write all prime implicants, (3) wirte all essential prime implicants, (4) write a minimal SoP cover, (5) write a minimal PoS cover, (5) use NAND gates to implement the circuit. (example only)
5. 4/9: f(a,b,c,d) = abc+bd+...., (1) write the K-Map, (2) write all prime implicants, (3) wirte all essential prime implicants, (4) write a minimal SoP cover, (5) write a minimal PoS cover, (5) use NAND gates to implement the circuit. (example only)
6. 4/18: Use (1) Decoder and NAND gate or (2) MUX to implement f(a,b,c)=m0+m1+m3+m5 (example, gate types or decoder type will be changed during the example).
7. 4/25: Design a (a) half adder (b) full adder or (c) iterative comparator.
8. 5/23: Draw the Circuit Diagram, Transition Diagram, and Excitation Table of (a) RS-Latch (b) Gated D-Latch (c) RS Flip-Flop (d) D Flip-Flop (e) JK Flip-Flop (f) T Flip-Flop. (two of the above)
9. 5/28: Problem 6.9, 6.10, 6.12, 6.13 on Page 427,428. (of of the abvoe)