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魏慶隆 博士 Chin-Long Wey, Ph.D. E-mail：clwey@ee.ncu.edu.tw 電話：(03)4227151 分機 34516 桃園縣中壢市五權里2鄰中大路300號 助理﹕ 電話：(03)4227151 分機 34578 |
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國立中央大學電機工程系教授 (2003~)
美國德州理工大學電機工 美國德州理工大學電腦科學碩士 (1980) 國立中央大學數學學士 (1973)
國家實驗研究院國家晶片系統設計中心主任 (2007-2010) 國立中央大學資訊電機學院院長 (2003-2006) 美國密西根州立大學電機及電腦系教授 (1983-2003) (20年) 智微科技股份有限公司(新竹)創任總經理 (2001-2002) 美國密西根州立大學電腦工程首屆主任 (1995-1997) 國立中央大學電機工程系客座教授(2000) 德國 Robert Bosch公司汽車電子系統Faculty Fellow
(1999) 國立交通大學電子工程系客座副教授(1990)
國際電機電子工程學會會士評議委員(電路與系統領域﹐CASS),
2011 國際電機電子工程學會會士評議委員(電腦科學領域﹐CSS),
2011 國際電機電子工程學會會士(IEEE
Fellow), 2011 發明專利“具有同時充放電功能之可程式化電池管理模組結構”榮獲“2011年台北國際發明暨技術交易展”銀牌獎 (2011) 國家實驗研究院傑出科技貢獻獎﹐技術發展類優等(2010) 國家實驗研究院傑出科技貢獻獎﹐學術研究類第一名(2009) 國家實驗研究院特聘研究員 (2007-2010) 國立中央大學台積電傑出講座教授 (2004, 2007) 國立雲林科技大學電子工程系國科會客座講座教授 (2003)
1.
整合式鋰電池充放電管理系統晶片設計與應用 2.
整合式車用網路控制器—FLEXRAY及其容錯系統設計 3.
IC Design for X-ability (X: reliability, diagnosability,
teatability, …) 4.
類比/混合訊號IC設計、測試、及可靠度分析 |
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List of
Publication Book Chapters 1.
C.L. Wey, C.-c. Wu, and R.
Saeks, "Analog Fault Diagnosis," Testing and Diagnosis of VLSI
and ULSI, Ed. by M. Sami and F. Lombardi, Kluwer Academic Publisher,
pp.117-150, 1988. 2.
F. Lombardi and C.L. Wey,
"On Front Reconfiguration of VLSI Arrays," Testing and Diagnosis
of VLSI and ULSI, Ed. by M. Sami and F. Lombardi, Kluwer Academic
Publisher, pp.429-468, 1988. 3.
C.L. Wey and R. Saeks,
"On the Implementation of Analog ATPG: The Linear Case," Analog
Fault Diagnosis, Edited by R.W. Liu, IEEE PRESS, 1989. 4.
C.L. Wey, "A Searching
Approach Self-Testing Algorithm for Analog Fault Diagnosis," Testing
and Diagnosis of Analog Circuits and Systems, Ed. by R.W. Liu, Van
Nostrand Reinhold, New York, pp.147-185, 1991. 5.
C.L. Wey, "Test
techniques for CMOS Switched-Current Circuits," Analog and
Mixed-Signal Test, Edited by B. Vinnakota, Prentice-Hall, Inc., 1998. Journal Papers 1
C.-c. Wu, K. Nakajima, C.L.
Wey, and R. Saeks, "Analog Fault Diagnosis with Failure Bounds,"
IEEE Trans. on Circuits and Systems, Vol. CAS-29, No.5, pp.277-284,
May 1982. 2
C.L. Wey and R. Saeks,
"On the Implementation of Analog ATPG: The Linear Case," IEEE
Trans. on Instrumentation and Measurement, Vol. IM-34, No.3,
pp.442-449, September 1985. 3
C.L. Wey, "A Decision
Process for Analog System Fault Diagnosis," IEEE Trans. on
Circuits and Systems, Vol. CAS-34, No.1, pp.107-109, January 1987. 4
C.L. Wey, M.K. Vai, and F.
Lombardi, "On the Design of a Redundant PLA," IEEE Journal of
Solid-State Circuits. Vol. SC-22, No.1, pp.114-117, February 1987. 5
C.L. Wey and F. Lombardi,
"On the Repair of Redundant RAM’s," IEEE Trans. on CAD of
Integrated Circuits and Systems. Vol. CAD-6, No.2, pp.222-231.
March, 1987. 6
C.L. Wey and F. Lombardi,
"On the Novel Self-test Approach to Digital Test," The
Journal of Computers, Vol.30, No.3, pp.258-267, March 1987. 7
C.L. Wey, "Design of
Testability for Analog Fault Diagnosis," International Journal of
Circuit Theory and Application, Vol.15, No.2, pp.123-142, April 1987.
8
F. Lombardi and C.L. Wey,
"Algorithms for Functional Testing of Digital Systems," (Invited
Paper) International Journal of Electronics, Vol.62, No.5,
pp.707-732, May 1987. 9
B.L. Jiang, C.L. Wey, and L.J
Fan, "Fault Prediction for Analog Circuits," Journal of
Circuits, Systems, and Signal Process. Vol.7, No.1, pp.95-109,
January 1988. 10
S.-W. Chan and C.L. Wey,
"The Design of Concurrent Error Diagnosable Systolic Arrays for
Band-Matrix Multiplication," IEEE Trans. on CAD of Integrated
Circuits and Systems (Special issue on Testable and Maintainable
Design), Vol. CAD-7, No.1, pp.21-37, January 1988. 11
S.-W. Chan, S.S. Leung, and
C.L. Wey, "A Systematic Design Strategy for Concurrent Error Diagnosable
Iterative Logic Arrays," IEE Proceedings, Part E, Computers and
Digital Techniques, Vol.135, No.2, pp.87- 94, March 1988. 12
C.L. Wey, "On Yield
Considerations for the Design of Redundant Programmable Logic Arrays," IEEE
Trans. on CAD of Integrated Circuits and Systems, Vol. CAD-7, No.4,
pp.528-535, April 1988. 13
C.L. Wey and R. Saeks,
"On the Implementation of Analog ATPG: The Nonlinear Case,"
IEEE Trans. on Instrumentation and Measurement, Vol. IM-37, No.2,
pp.252-258. June 1988. 14
C.L. Wey, "Parallel
Processing for Analog Fault Diagnosis," International Journal of
Circuit Theory and Application, Vol.16, pp.303-316, July 1988. 15
B.L. Jiang, and C.L. Wey,
"Fault Prediction Process for Large Analog Circuit Networks," International
Journal of Circuit Theory and Applications. Vol.17, No.2,
pp.141-149, April 1989. 16
C.L. Wey and S.M. Chang,
"Test Generation for C-testable Array Dividers," IEE
Proceedings, Part E, Computers and Digital Techniques, Vol.136,
No.5, pp.434-442, September 1989. 17
T.Y. Chang and C. L. Wey,
"Design of fault diagnosable and repairable PLA," IEEE
Journal of Solid-State Circuits. Vol. SC-24, No.5, pp.1451-1454,
October 1989. 18
C.L. Wey, and T.Y. Chang,
"An Efficient Output Phase Assignment for PLA Minimization," IEEE
Trans. on CAD of Integrated Circuits and Systems, Vol.9, No.1,
pp.1-7, January 1990. 19
C.L. Wey, "Built-In
Self-Test (BIST) Structure for Analog Circuits Fault Diagnosis,"
IEEE Trans. on Instrumentation and Measurement. Vol. IM-39, No.2,
pp.517-521, June 1990. 20
C.L. Wey and T.Y. Chang,
"Design of VLSI-Based Parallel Multipliers," IEE Proceedings,
Part E, Computers and Digital Techniques. Vol.137, No.4, pp.328-336,
July1990. 21
B.L. Jiang and C.L. Wey,
"Fault Prediction for Analog Circuits - Reply," Journal of
Circuits, Systems, and Signal Process. Vol.9, No.4, p.503, 1990. 22
C.L. Wey, T.Y. Chang, and
J.Y. Ding, "Design of Fault Diagnosable and Repairable Folded PLAs for
Yield Enhancement," IEEE Journal of Solid-State Circuits.
Vol.26, No.1,pp.54-57, January 1991. 23
C.L. Wey, "Alternative
Built-In Self-Test Structure (BIST) for Analog Circuit Fault Diagnosis,"
Electronics Letters. Vol.27, No.18, pp.1627-1628, August 1991. 24
C.L. Wey, "Concurrent
Error Detection in Current-Mode A/D Converter," Electronics
Letters. Vol.27, No.25, pp.2370-2372, December 1991. 25
C.L. Wey, "Concurrent
Error Detection in Array Dividers by Alternating Input Data," IEE
Proceedings, Part E, Computers and Digital Techniques. Vol.139, No.2,
pp.123-130, March 1992. 26
C.L. Wey and S. Krishnan,
"An Accurate Current-mode Divide-by-two Circuit," Electronics
Letters. Vol.28, No.9, pp.820-822, April 1992. 27
C.L. Wey and S. Krishnan,
"Built-In Self-Test (BIST) Structures for Analog Circuit Fault Diagnosis
with Current Test Data," IEEE Trans. on Instrumentation and
Measurement, Vol. IM-41, No.4, pp.535-539, August 1992. 28
C.L. Wey, S. Krishnan,, and 29
S. Krishnan, and C.L. Wey,
"An Accurate Reference-generating Circuit for Successive Approximation
Current- mode A/D Converters," International Journal of Circuit
Theory and Application. No.21, pp.361-369, August 1993. 30
M.-D. Shieh, C.L. Wey, and
P.D. Fisher, "Fault Effects in Asynchronous Sequential Logic
Circuits," IEE Proceedings, Part E, Computers and Digital
Techniques. Vol. 140, No.6, pp.327-332, November 1993. 31
J.-W. Kang, P.D. Fisher, and
C.L. Wey, "An Efficient Modeling and Synthesis Procedure of Asynchronous
Sequential Logic Circuits," IEE Proceedings, Part E, Computers and
Digital Techniques. Vol.141, No.1, pp. 61-64, January 1994. 32
C.L. Wey, 33
C.-S. Lai and C.L. Wey,
"SOLiT: An Automated system for Synthesizing Reliable Sequential
Circuits with Multi-level Logic Implementation," IEE Proceedings,
Computers and Digital Techniques, Vol.142, No.1, pp.49-54, January
1995. 34
R. Huang and C.L. Wey, "Simple
Yet Accurate Current Copiers for Low-Voltage Current-Mode Signal Processing
Applications," International Journal of Circuit Theory and
Application, vol.23, pp.137-145, No.2, March 1995. 35
C.L. Wey, "Design and
Test Generation of C-testable High Speed Dividers," IEE
Proceedings, Computers and Digital Techniques,.Vol.142, No.3,
pp.193-200, May 1995. 36
J.-W. Kang, C.L. Wey, and
P.D. Fisher, "Applications of Bipartite Graphs for 37
C.L. Wey, S. Krishnan,, and
S. Sahli, "Test Generation and Concurrent Error Detection in
Current-Mode A/D Converters," IEEE Trans. on CAD, Vol. 14,
No.10, pp. 1291-1298, October 1995. 38
R. Huang and C.L. Wey,
"Simple Low-voltage, High-speed, High-linearity V-I Converter with S/H
for Analog Signal Processing Applications," IEEE Trans. on
Circuits and Systems. Part II. Analog and Digital Signal Processing. Vol.43,
No.1, pp.52-55, January 1996. 39
C.L. Wey, "Built-in
Self-test (BIST) Design of High-speed Carry-free Dividers," IEEE
Trans. on VLSI Systems, Vol. 4, No. 1, pp. 141-145, March 1996. 40
R. Huang and C.L. Wey,
"Design of High-speed, High-accuracy Current Copiers for Low-voltage
Analog Signal Processing Applications," IEEE Trans. on Circuits
and Systems, Part II. Analog and Digital Signal Processing. Vol.43,
No.12, pp.836-839, December 1996. 41
C.L. Wey, "Built-in
Self-test (BIST) Design of Current-mode Algorithmic A/D Converter," IEEE
Trans. on Instrumentation and Measurement. Vol. 46, No. 3,
pp.667-671, June 1997. 42
T.-H. Pan and C.L. Wey,
"GRASS: an Efficient Gate Re-assignment Algorithm for Inverter
Minimization in Post Technology Mapping," IEE Proceedings,
Computers and Digital Techniques. Vol. 144, No.5, pp.348- 352,
September 1997. 43
C.-P. Wang and C.L. Wey,
"Fault Macromodel for Switches in Switched-current Circuits," International
Journal of Circuit Theory and Applications. Vol. 26, pp.93-102.
January 1998. 44
R. Huang and C.L. Wey,
"A High-performance CMOS Oversampling Current Sample/Hold (S/H) Circuit
Using Feedforward Approach," IEEE Trans. on Circuits and Systems,
Part II. Analog and Digital Signal Processing, Vol. 45, No.3, pp.
395-399. March 1998. 45
W.-H. Huang, and C.L. Wey,
"ATPRG: An Automatic Test Program Generator Using HDL-A for Fault Diagnosis
of Analog/Mixed-signal Integrated Circuits," IEEE Trans. on
Instrumentation and Measurement., Vol. 47, No. 2, pp.426-431, April
1998. 46
W.-H. Huang and C.L. Wey,
"Diagnosability Analysis of Analog Circuits," International
Journal of Circuit Theory and Application. Vol. 26, No.5, pp.439-451,
September 1998. 47
C.L. Wey and M.-D. Shieh,
"Design of High-speed Square Generator," IEEE Trans. on
Computers. Vol.47, No. 9,
pp.1021-1026, September 1998. 48
J.-S. Wang and C.L. Wey,
"Design and Analysis of High Performance Current Reference Generators
for Low-power CMOS Data Converters," IEEE Trans. on Circuits and
Systems, Part II. Analog and Digital Signal Processing. Vol.46, No.5,
pp.647-652, May 1999. 49
J.-S. Wang and C.L. Wey,
"A 12-bit, 100ns/b, 1.9mW CMOS Switched-current Cyclic A/D
Converter," IEEE Trans. on Circuits and Systems, Part II. Analog
and Digital Signal Processing, Vol.46, No.5, pp.507- 516, May 1999 50
Y. Wan and C.L. Wey,
"Efficient Algorithms for Binary Logarithmic Conversion and
Addition," IEE Proceedings, Computers and Digital Techniques.
Vol.146, No.3, pp.168-176, May 1999. 51
C.L. Wey and C.-P. Wang,
"A Fast Radix-4 SRT Divider and Its VLSI Implementation," IEE
Proceedings, Computers and Digital Techniques. Vol. 146, No.4,
pp.205-210, July 1999. 52
C.L. Wey and W.-H. Huang,
"Designability Check for Analog Circuits with Incomplete Implementation
Information," IEEE Trans. on Circuits and Systems, Part I,
Fundamental Theory and Applications. Vol. 46, No.8, pp.939-949,
August 1999. 53
Y. Wan, M.A. Khalil, and C.L.
Wey, "Efficient Conversion Algorithms for Long-word-length Binary Logrithmic
Numbers and Hardware Implementation," IEE Proceedings, Computers
and Digital Techniques. Vol. 146, No.6, pp.295-301, November 1999. 54
R. Huang, J.-S. Wang, and
C.L. Wey, "A Fully Differntial Current Copier for Performance
Improvement," International Journal of Circuit Theory and Application.
Vol. 28, No.2, pp. 101-108, March 2000. 55
C.-P. Wang and C.L. Wey,
"Design of High performance Current Comparator as Built-in Testers of
CMOS Switched-current
Circuits," International Journal of Analog Integrated
Circuits and Signal Processing, Vol.23, No.3, pp.179-188, June 2000. 56
C.L. Wey, "Design of
Fast High-radix SRT Dividers and Their VLSI Implementation," IEE
Proceedings, Computers and Digital Techniques, Vol.147, No.4, pp.275-282,
July 2000. 57
C.L. Wey, “ReSTRO: Efficient
Rectlinear Steiner Tree Construction with Rectangular Obstacles,” WSEAS
Trans. on Circuits and Systems, Vol.5,
pp.1768-1774, December 2006. 58
C.L. Wey, S.-Y. Lin, T.-H.
Tsai, and M.T. Shiue, “Efficient Implementation of Interpolation Technique for Symbol Timing Recovery
in DVB-T Transceiver Design,”
WSEAS Trans. on Circuits and Systems, Vol. 6, pp.215-221, January 2007. 59
C.L. Wey and S.-Y. Lin, “An
Efficient Pipelined Divider with a Small Lookup Table,” WSEAS Trans. on
Electronics, Vol. 4, pp.56-52,
March 2007. 60
C.L. Wey, C.-S. Huang, and S.
Quan, “Design of Reliable CMOS Phase Locked Loops,” International Journal of Electrical Engineering, Vol.14, No.3,
pp.195-206, 2007. 61 P.-W. Luo, J.-E. Chen, C.L. Wey, L.-C. Cheng, J.-J. Chen, and
W.-C. Wu, “Impact of Capacitance Correlation on Yield Enhancement of
Mixed-signal/Analog Integrated Circuits,” IEEE Trans. on CAD of
Integrated Circuits and Systems, Vol. 27, No.11, pp.2097-2101,
November 2008. 62 P.-W. Luo, J.-E. Chen, and C.L. Wey, “Yield Evaluator of
Mixed-Signal Circuit Using Spatial Correlation Analysis,” SoC
Technical Journal, Vol. 9, pp. 87-95, December 2008. 63
C.L.
Wey, M.-D. Shieh, and S.-Y. Lin, “Efficient Algorithm and Hardware
Implementation of Finding First Two Minimum Values for LDPC Decoding
Applications,” IEEE Trans. on
Cicuits and Systems I, Vol. 55, pp.3430-3437, December 2008. 64
C.-S. Lin, T.-H. Chien, C.L.
Wey, C.-M. Huang, and Y.-Z. Juang, “An Edge Missing Compensator for Fast
Settling Locked Range Phase-locked Loops,” IEEE Journal of Solid-State Circuits, Vol.44, No.11,
pp.3102-3110, November 2009. 65
J.-E. Chen, P.-W. Luo, and
C.L. Wey, ”Placement Optimization for Yield Improvement of Switched-capacitor
Analog Integrated Circuits,” IEEE
Trans. on Computer CAD of Integrated Circuits and Systems, Vol.29, No.2, pp.313-318, February 2010.
66
C.-C. Wang, G.-N. Sung,
P.-C., Chen, and C.L. Wey, “A Transceiver Frontend for Electronic Control Units
in FlexRay-based Automotive Communication Systems,” IEEE Trans. on Circuits and
Systems, I: Regular Papers, Vol. 57, No. 2, pp.460-470, February 2010. 67
C.-M.
Huang, Y.-T. Chang, J.-Y. Hsieh, C.-M. Wu, H.-T. Wu, C.-Y. Lin, J.-J. Wang,
and C.L. Wey, “MorFPGA: A Modularized FPGA Development Platform for IC Design
Education,” Innovations 2010: World Innovations in Engineering
and Research, pp.197-212, August 2010. 68
S.-Y. Lin, C.L. Wey and M.-D.
Shieh, “Low-Cost FFT Processor for DVB-T2 Applications,” IEEE Trans. on
Consumer Electronics, Vol.56, No.4, pp.2072-2079, November 2010. 69
C.L. Wey, S.-Y. Lin, H.-S.
Wang, H.-L. Cheng, and C.-M. Huang, “A Low-cost Continuous-flow Parallel
Memory-based FFT Processor for UWB Applications,” IEICE Trans. on
Fundamentals of Electronics, Communications and
Computer Sciences, Vol. E94-A, No.1, pp.315-323, January 2011. 70
P.-W.
Luo, J.-E. Chen, M.-Y. Huang, and C.L. Wey, “Design Methodology for Yield
Enhancement of Switched-capacitor Analog Integrated Circuits,” IEICE Trans. on Fundamentals of Electronics, Communications and
Computer Sciences,
Vol. E94-A, No.1, pp.352-361, January 2011. 71 C.-M. Huang, C.-M.
Wu, C.-C. Yang, S.-L. Chen, C.-S. Chen, J.-J. Wang, K.-J. Lee, and C.L. Wey,
“Programmable System-on-chip (SoC) for Silicon Prototyping,” IEEE
Trans. on Industrial Electronics, Vol. 58, No.3, pp.830-838, March
2011. 72 C.L. Wey, S.-Y.
Lin, P.-Y.Tsai, and M.-D. Shieh,“Reconfigurable Homogenous
Multi-core FFT Processor Architectures for Hybrid SISO/MIMO OFDM
Wireless,” IEICE Trans. on Fundamentals of
Electronics, Communications and Computer Sciences, vol. E94-A, No. 7,
pp. 1530-1539, July 2011. 73 C.-M. Lu and C.L. Wey, “A Controller Design
for Micro-capsule Active Matrix Electrophoretic Dsiplays,” IEEE Journal
of Display Technology, Vol. 7, No. 8, pp.434-442, August 2011. 74 C.-M. Lu and C.L. Wey, “A Controller
Design for Color Displays Using Electrophoretic Inks and Color Filters,” IEEE
Journal of Display Technology. Vol. 7, No. 9, pp.482-489, September
2011. 75
C.-S. Lin, T.-H. Chien, and
C.L. Wey, “A 5.5GHz, 1mW, Full-modulus-rang Programmable Frequency Divider in
90nm CMOS Process,” IEEE Trans. on Circuits and Systems II,
Vol. 58, No.9, pp.550-554, September 2011. 76
C.-M. Lu and C.L. Wey, “A Controller
Design for Micro-Cup Active Matrix Electrophoretic Displays,” Journal
of the Society for Information Display, pp.103-108, February 2012 77
C.-M. Lu and C.L. Wey, “A Controller
Design for High Quality Images on Micro-Capsule Active Matrix Electrophoretic
Displays,” Journal of Information Display, issue 13(1), pp.21-30, March
2012. Conference
Papers 1. C.-c. Wu, K. Nakajima, C.L. Wey,
and R. Saeks, "Analog fault diagnosis with failure bounds," Proc.
24th Midwest Symp. on Circuits and Systems, 2. C.L. Wey, D. Holder, and R. Saeks,
"On the Implementation of an Analog ATPG," Proc. IEEE 3rd Automatic
Test Program Generation (ATPG) workshop, pp.33-36, 3. C.L. Wey, D. Holder, and R. Saeks, "On
the Implementation of an Analog ATPG," Proc. IEEE international Symp. on
Circuits and Systems, 4. C.L. Wey and R. Saeks, "On the Implementation
of Analog ATPG II," IEEE 4th Automatic Test Program Generation (ATPG)
workshop, 5. C.L. Wey and R. Saeks, "On the
Implementation of an Analog ATPG: The Nonlinear Case," Proc. IEEE International
Symp. on Circuits and Systems, 6. C.L. Wey, "Parallel Processing for
Analog Fault Diagnosis," Proc. 27th 7. C.L. Wey, "UUT Modeling for Digital Test
- A Self-test Approach," Proc. IEEE Fourth Annual Phoenix Conference on
Computers and Communications, 8. C.L. Wey, "Design of Testability for
Analog Fault Diagnosis," Proc. IEEE International Symp. on Circuits and
Systems, 9. F. Lombardi and C.L. Wey, "Fault
Identification Algorithm for VLSI Systems," Proc. ICCD, International
Conference on Computer Design: VLSI in Computers, 10. F. Lombardi
and C.L. Wey, "On a Multiprocessor System with Dynamic Redundancy,"
Proc. Real-Time Systems Symposium, 11. F. Lombardi
and C.L. Wey, "Diagnosis and Fault Identification Algorithms for Large
Scale Computing Systems," Proc. First International Conference on
Supercomputing Systems, 12. C.L. Wey
and F. Lombardi, "On a New Decision Process for t-diagnosis of an Analog
System," Proc. IEEE International Symp. on Circuits and Systems, 13. B.L. Jiang
and C.L. Wey, "Multiple Fault Diagnosis with Failure Bound for Analog
Circuits," Proc. IEEE International Symp. on Circuits and Systems, 14. C.L.
Wey and F. Lombardi, "On the Repair of Programmable Logic Arrays,"
Proc. IEEE International Symp. on Circuits and Systems, 15. C.L.
Wey, T.Y. Chang, and M.K. Vai, "On the Design of Fault-Tolerant
Programmable Logic Arrays," Proc. International Computer Symp., 16. C.L.
Wey, "An Efficient Unrepairability Detection Scheme for Redundant RAM
Test System," Proc. International Computer Symp., 17. C.L.
Wey and F. Lombardi, "Efficient, Yet Simple Algorithms for Repairing
Redundant RAMs," Proc. IEEE International Symp. on Circuits and Systems,
18. C.L.
Wey and F. Lombardi, "Analysis and Design of Repairable PLAs,"
Proc. CompEuro, pp.363-366, May 1987. 19. C.L.
Wey, "On Yield Considerations for the Design of Redundant Programmable
Logic Arrays," Proc. ACM/ IEEE Design Automation Conference (DAC),
pp.622-628, June 1987. 20. B.L.
Jiang and C.L. Wey, "Fault Prediction Process for Large Analog Circuit
Networks," Proc. 30th 21. C.L.
Wey, T.Y. Chang, and Y.F. Chen, "The Design of VLSI-based Parallel
Multipliers," Proc. 30th 22. S.M.
Chang and C.L. Wey, "Test Generation for C-testable Array
Multipliers," Proc. 25th Allerton Conference, 23. C.L.
Wey and T.Y. Chang, "Minimization of PLAs with Ground True
Outputs," Proc. of 25th ACM/IEEE Design Automation Conference (DAC), 24. T.Y.
Chang and C.L. Wey, "Design and Test of Electrically Field-Repairable
APLAs," Proc. 31st 25. C.L.
Wey and T.Y. Chang, "An Efficient Boolean Comparison Process for Logic
Verification," Proc. 31st 26. C.L.
Wey, B.L. Jiang, and G. Wierzba, "Built-In Self-Test for Analog Circuit
Networks," Proc. 31st 27. C.L.
Wey and S.-M. Chang, "Built-in Self-test (BIST) Design of C-testable Baugh-Wooley
Array Multiplier," Proc. 31st 28. C.L.
Wey and S.-M. Chang, "Test Generation of C-testable Array
Dividers," Proc. IEEE International Conference on Computer Design: VLSI
in Computers & Processors (ICCD ’88), 29. C.L.
Wey, and B.L. Jiang, "Built-in Self-test (BIST) Design of Large Scale
Analog Circuit Networks," Proc. 1989 IEEE International Symp. on
Circuits and Systems, 30. C.L.
Wey, S.-M. Chang, and J.-Y. Jou, "An Efficient Output Phase Assignment
for MultiLevel Logic Minimization," Proc. 1989 International Workshop
on Logic Synthesis, 31. C.L.
Wey, "Fault Location in Repairable Programmable Logic Arrays," Proc. IEEE International Test Conference
(ITC), 32. C.L.
Wey, S.-M. Chang, and J.-Y. Jou, "OPAM: An Efficient Output Phase
Assignment for Multilevel Logic Minimization," Proc. IEEE International
Conference on Computer Design: VLSI in Computers & Processors (ICCD ’89),
33. C.L.
Wey, "Output Phase Assignment for Logic Minimization," (invited),
2nd Workshop on CAD for VLSI, 34. C.L.
Wey, J. Ding, and T.-Y. Chang, "Design of Repairable and Fully
Diagnosable Folded PLAs for Yield Enhancement," Proc. 27th ACM/IEEE Design Automation Conf. (DAC),
35. C.L.
Wey and J. Ding, "Design of Repairable and Fully Testable Folded PLAs
for Yield Enhancement," Proc. IEEE International Conference on Computer
Design: VLSI in Computers & Processors (ICCD ’90), 36. C.L.
Wey and T.-Y. Chang, "On the Design of Concurrent Error Detectable
Multiply and Divide Arrays," Proc. International Computer Symposium, 37. C.L.
Wey, "Concurrent Error Detection in Array Dividers by Alternating Input
Data," Proc. IEEE International Conference on Computer Design: VLSI in
Computers & Processors (ICCD ’91), 38. C.L.
Wey, M.-D. Shieh, and P.D. Fisher, "On Synthesis for Testability of
Asynchronous Sequential Logic Circuits," IFIP International Workshop on
the Relationship between Synthesis, Test, and Verification. 39. C.-S.
Lai, and C.L. Wey, "An Efficient Algorithm for Reducing Hardware
Overhead in Self-checking Circuits and Systems," Proc. 35th 40. J.-W.
Kang, C.L. Wey, and P.D. Fisher, "An Efficient Modelling and Synthesis
Procedure of Asynchronous Sequential Logic Circuits," Proc. 35th 41. M.-D.
Shieh, C.L. Wey, and P.D. Fisher,"Model of Asynchronous 42. S.
Krishnan, S. Sahli, and C.L. Wey, "Test Generation and Concurrent Error
Detection in Current-mode A/D converters," Proc. IEEE International Test Conference (ITC), 43. S.
Sahli, S. Krishnan, and C.L. Wey, "Design of Concurrent Error Detectable
Current-Mode A/D converters," Proc. International Conference on 44. J.-W.
Kang, C.L. Wey, and P.D. Fisher, "Race-free State Assignments Using
Bipartite Graphs," Proc. of IEEE Symposium on Circuits and Systems, 45. M.-D. Shieh, C.L. Wey, and P.D.
Fisher, "Scan Design for Asynchronous Sequential Logic Circuits Using
SR-latches," Proc. 36th Midwest Symp. on Circuits and Systems, 46. J.-W. Kang, C.L. Wey, and P.D.
Fisher, "A Synthesis Procedure for Large-Scale Asynchronous 47. C.-S. Lai and C.L. Wey,
"Design of Fast, Yet Low Hardware Cost Self-testing Berger Code
Checkers," Proc. 36th 48. C.L. Wey, M.-D. Shieh, and P.D.
Fisher, "ASLCScan: A Scan Design Technique for Asynchronous Sequential
Logic Circuits," Proc. IEEE International Conference on Computer Design:
VLSI in Computers & Processors (ICCD ’93), 49. R. Huang and C.L., Wey, "A
Simple Yet Accurate Current Copier," Proc. 37th 50. C.L. Wey, "Design of
C-testable High Speed Dividers," Proc. 37th Midwest Symp. on Circuits
and Systems, 51. S. Krishnan and C.L. Wey, "A
Parallel Current-mode A/D Converter Array with a Common Current Reference-Generating
Circuit," Proc. 37th Midwest Symp. on Circuits and Systems, 52. C.L. Wey, "Concurrent Error
Detection in High Speed Carry-free Dividers," Proc. IEEE International
Conference on Computer Design: VLSI in Computers & Processors (ICCD
’94), 53. R. Huang and C.L. Wey,
"High-speed, Low-voltage V-I Converters for Analog Signal Processing
Applications," IEEE Asia-Pacific Conference on Circuits and Systems
(APCCAS’ 94), 54. C.L. Wey, "Built-in
Self-test (BIST) Design of High-speed Carry-free Dividers," Proc. IEEE
Symposium on Circuits and Systems, 55. C.L. Wey, A.Y. Tetelbaum, and T.
Bickart, "A Performance-driven Placement Approach of Standard
Cells," Proc. International Conference on Intelligent Systems, 56. C.L. Wey, H. Wang, and C.-P.
Wang, "A Self-timed Redundant-Binary to Binary Number Converter for
Digital Arithmetic Processors," Proc. IEEE International Conference on
Computer Design: VLSI in Computers & Processors (ICCD ’95), 57. T.-H. Pan.H.-S. Kay, Y. Chun, and
C.L. Wey, "High-radix SRT Division with Speculation of Quotient Digits,"
Proc. IEEE International Conference on Computer Design: VLSI in Computers
& Processors (ICCD ’95), 58. R. Huang and C.L. Wey, "A
High-accuracy CMOS Oversampling Current Sample/Hold (S/H) Circuit Using
Feedforward Approach," Proc. IEEE International Symposium on Circuits
and Systems, 59. R. Huang and C.L. Wey, "A
5mW, 12-b, 50ns/b Switched-current Cyclic A/D Converter," Proc. IEEE
International Symposium on Circuits and Systems, 60. C.-P. Wang, A.A. Hatzopoulos, and
C.L. Wey, "A Test Paradigm for Analog and Mixed-signal Circuits and
Systems," Proc. IEEE International Symposium on Circuits and Systems,
Atlanta, GA, Vol. III, pp. 194-197, May 1996. 61. C.-P. Wang and C.L. Wey,
"Test Generation of Switched-current A/D Converters," Proc. 2nd
IEEE International Mixed Signal Testing Workshop, Quebec City, Canada, pp.
98-103, May 1996. 62. R. Huang, C.-P. Wang, C. Grunewald, and C.L.
Wey, "Design of High-accuracy CMOS Oversampling Current Sample/Hold
(S/H) circuits," Proc. of 39th Midwest Symp. on Circuits and Systems, 63. C.L. Wey and C.-P. Wang,
"VLSI Implementation of a Fast Radix-4 SRT Division," Proc. of 39th
64. T.H. Pan and C.L. Wey, "An
Efficient Gate Re-assignment Algorithm in Post Technology Mapping,"
Proc. of 39th 65. C.L. Wey, "On Design of
Efficient Square Generator," IEEE International Conference on Computer
Design: VLSI in Computers & Processors (ICCD ’96), 66. C.L. Wey, "Mixed-signal
Testing -- a Review," (invited) IEEE International Conference on
Electronics, Circuits, and Systems, 67. C.-P. Wang and C.L. Wey,
"Test Generation of Analog Switched-current Circuits," Proc. Asian
Test Symposiums, 68. C.-P. Wang and C.L. Wey,
"Efficient Testability Design Methodologies for Mixed-signal/Analog
Integrated Circuits," 3rd IEEE International Mixed Signal Testing
Workshop, Seattle, WA, pp. 68-74, June 1997. 69. W.-H. Huang and C.L. Wey,
"Development of HDL-A Modeled Test Programs for Fault Diagnosis of
Analog/Mixed-signal Circuits," 3rd IEEE International Mixed Signal
Testing Workshop, Seattle, WA, pp. 3-14, June 1997. 70. R. Huang, J.-S. Wang, and C.L.
Wey, "A Fully Differential Switched-Current ADC with Improved Performance,"
(invited) Proc. 40th Midwest Symp. on Circuits and Systems, 71. C.L. Wey, "Development of
Redesign Process for Digital VLSI Systems," Proc. 40th 72. C.-P. Wang and C.L. Wey,
"High-accurate CMOS Current Comparator," Proc. 40th 73. W.-H. Huang and C.L. Wey,
"Development of Automatic Test System for Mixed-signal/Analog Integrated
Circuits," Proc. 40th 74. C.-P. Wang and C.L. Wey,
"Development of Hierarchical Testability Design Methodologies for
Mixed-signal/Analog Integrated Circuits," Proc. International
Conference on Computer Design (ICCD) , pp.468-473, October 1997. 75. M. Jimenez, M. Shanblatt, and
C.L. Wey, "Mapping Multiplication Algorithms into a Family of LUT-based
FPGAs," 1998 ACM/SIGDA Sixth International Symposium o Field
Programmable Gate Arrays (FPGA'98), Monterey, CA, February 1998. 76. M.A. Khalil and C.L. Wey,
"Using Test Generation Techniques for Redesigning Digital VLSI Circuits
with Incomplete Implementation Information," Proc. International
Conference on Chip Technology, 77. J.-S. Wang and C.L. Wey,
"Accurate CMOS Switched-current Divider Circuits," Proc. IEEE
International Symposium on Circuits and Systems, 78. J.-S. Wang and C.L. Wey, "A
12-bit, 100ns/b, 1.9mW CMOS Switched-current Cyclic A/D Converter,"
Proc. IEEE International Symposium on Circuits and Systems, 79. Y. Wan and C.L. Wey,
"Efficient Algorithms for Binary Logarithmic Conversion and
Addition," Proc. IEEE International Symposium on Circuits and Systems, 80. C.L. Wey and M.A. Khalil,
"Redesignability Analysis of Digital VLSI Circuits with Incomplete
Implementation Information," Proc. IEEE International Symposium on
Circuits and Systems, 81. J.-S. Wang, W.-H. Huang, and C.L.
Wey, "Built-In Testers for Analog/Mixed-Signal Circuits with CMOS
Switched-Current Technique" Proc. of 4th IEEE International Mixed-Signal
Workshop, 82. M.A. Khalil and C.L. Wey,
"Redesign Strategies for Digital VLSI Circuits with Incomplete
Implementation Information," IEEE Midwest Symposium on Circuits and
Systems, Notre Dame, IN, pp.264-267, August 1998. 83. J.-S. Wang and C.L. Wey, "A
10-b, 100MS/s, 2.8mW CMOS Switched-current DAC for Low-power/Low-voltage
Signal Processing Applications," Proc. IEEE Midwest Symposium on
Circuits and Systems, Notre Dame, IN, pp.526-529, August 1998. 84. W.-H. Huang, J.A. Resh, and C.L.
Wey, ""On Synthesis of Manufacturable and Testable Analog
Integrated Circuits," Proc. IEEE Midwest Symposium on Circuits and
Systems, Notre Dame,IN, pp.340-343, August 1998 85. J.-S. Wang, R. Huang, and C.L.
Wey, "Synthesis of Optimal Current Copiers for Low-power/Low-voltage
Switched-current Circuits," Proc. IEEE Midwest Symposium on Circuits and
Systems, Notre Dame, IN, pp.220-223, August 1998. 86. J.-S. Wang, W.-H. Huang, and C.L.
Wey, "Fault Simulation of Built-in Tester for CMOS Switched-current
Circuits," Proc. IEEE Midwest Symp. on Circuits and Systems, Notre Dame,
IN, pp. 212-215, August 1998.. 87. J.-S. Wang, and C.L. Wey,
"Design of High-performance CMOS Switched-current D/A Converters for
Low- power/Low-voltage Signal Processing Applications," Proc. IEEE
International Conference on Electronics, Circuits, and Systems, 88. C.L. Wey and W.-H. Huang,
"Test Point Selection Process and Diagnosability Analysis for Analog
Integrated Circuits," Proc. IEEE International Conference on Computer
Design: VLSI in Computers & Processors (ICCD ’98), 89. C.L. Wey, D.M. Aslam, and B. Kim,
"Development of Embedded Testers Using Nano-Probes for Mnaufacturability
Enhancement of Microelectronic Circuits and Systems", presented in DAPRA
Tri-Service MEMS Based INSs Workshop, Alabama, December 1998. 90. J.-S. Wang and C.L. Wey, "A
11-b, 100MS/s, 4.4mW CMOS Switched-current Digital-to-Analog Converter,"
Proc. IEEE Midwest Symposium on Circuits and Systems, 91. J.-S. Wang and C.L. Wey,
"Built-in Testers for Analog/Mixed-siganl Circuits with CMOS
Switched-current Data Converters Techniques," Proc. IEEE E/IT
Conference, 92. M.A. Khalil and C.L. Wey,
"REDCI3: Redesignability Check for Digital VLSI Circuits with Incomplete
Implementation Information," Proc. IEEE Midwest Symp. on Circuits and
Systems, 93. D.T. Rover, B. Cheng, C.L. Wey,
and M. Mutka, "Incorporating Large-scale Projects into a Multi-disciplinary
Approach to Embedded Systems," Proc. International Conference on
Engineering Education, 94. J.-S. Wang and C.L. Wey, "A
Low-voltage Low-power 13b Pipelined Switched-current Cyclic A/D Converter,"
Proc. the IEEE 2nd Dallas CAS Workshop on Low Power and Low Voltage Analog
and Mixed Signal Circuits & Systems, Dallas, Texas, March, 2001. 95.
M.A.
Khalil and C.L. Wey, "High-voltage Stress Test Paradigms of Analog CMOS
ICs for Gate-oxide Reliability Enhancement," Proc. IEEE VLSI Test Symposium, 96.
M.A.
Khalil and
C.L. Wey, “Extreme-voltage Stress Vector Generation of Analog CMOS ICs for
Gate-Oxide Reliability Enhancement,” Proc. International Test Conference (ITC), 97. C.L. Wey, “Design for Stressability of
Analog CMOS ICs for Gate-oxide Reliability Enhancement.” IEEE International
Mixed-Signal Workshop, June, 2003. 98.
C.L. Wey, “High-speed IC/SOC Design at 99.
C.L. Wey, M.A. Khalil, J. Liu, and G. Wierzba,
“Hierarchical Extreme-voltage
Stress Test of Analog CMOS ICs for Gate-oxide Reliability Enhancement,” Proc.
Great 100.
S.
Quan and C.L. Wey, “A Noise Optimization Technique for Codesign of CMOS
Radio-frequency Low Noise Amplifiers and Low-quality Spiral Inductors,” Proc.
Great 101.
J.-F.
Li, C.-C. Hsu., Huang, C.-D., and C.L. Wey, “Soft IP Generation for
Reconfigurable Fast Adders,” Proc. Of 15th VLSI/CAD, 102.
C.L.
Wey, and M.Y. Liu, “Stress Test Pattern Generation for Analog CMOS ICs,”
Proc. of 15th VLSI/CAD, 103.
J.-F.
Li, Tseng, T.-W., Huang, J.-H, Yu, J.-D., and C.L. Wey, “Design of Reconfigurable Hybrid
Carry-lookahead/Carry-select Adders,” Proc. of 15th VLSI/CAD, 104.
Wey,
C,L, and M.Y. Liu, “Burn-in Stress Test of Analog ICs,” Proc. of Asian Test 105.
J.-F. Li, Y.-C. Kuo, C.-D. Huang, T-W. Tseng, and C.L. Wey, “Design of
Reconfigurable Carry Select Adders,” IEEE Asia-Pacific Conference on Circuits
and Systems, 106.
C.L.
Wey and J.-F. Li, “Design of Reconfigurable Array Multipliers and
Multiplier-accumulators,” IEEE Asia-Pacific Conference on Circuits and
Systems, 107.
J.-F. Li, T.-W. Tseng, and C.L. Wey,”An Efficient
Transparent Test Scheme for Embedded Memories”, Proc. Design, Automation and
Test in Europe (DATE), 108.
S.
Quan and C.L. Wey, “A Novel Reconfigurable Architecutre of Low-power
Multiplier for Digital Signal Processing,” Proc. of IEEE International Symp.
on Circuits and Systems, 109.
C.L. Wey, M.-Y. Liu, and S. Quan,
“Stress Test of CMOS SRAMs for Reliability Enhancement,” Proc. of IEEE
International Mixed-Signal Test Workshop (IMSTW), 110.
C.L. Wey, M.-Y. Liu, and S. Quan,
“Reliability Enhancement of CMOS SRAMs,” Proc. of IEEE International Workshop
on Memory Technology, Design, and Testing (MTDT), Taipei, Taiwan, pp.146-151,
August 2005. 111.
S.
Quan and C.L. Wey, “Design of a CMOS Operational Amplifier Amenable to
Extreme Voltage Stress,” Proc. of the 16th VLSI Design/CAD
Symposium, 112.
S.-F.
Lin, M.-T. Shiue, and C.L. Wey, “An Efficient Interpolation Strcuture for
Symbol Timing Recovery ,” Proc. of the 16th VLSI Design/CAD
Symposium, 113.
A.
Wey, Y.-B. Sun, and C.L. Wey, “Infrared-irradiated Fuel for Increased Fuel
Conversion Efficiency,” AFS Society, International Topical Conferences &
Exposition on Diesel and Gas Engine Emission Soultion, Ann Arbor, Michigan,
September 2005. 114.
115.
C.L. Wey, “Nanoelectronics:
Silicon Technology Roadmap and Emerging Nanoelectronics
Technology in 116.
S. Quan, Q. Qiang,
and C.L. Wey, “Design of a CMOS Operational Amplifier for Extreme-voltage
Stress Test,” Proc. of IEEE 14th Asian Test Symposium, 117.
M.-T.
Shiue and C.L. Wey, “Efficient Implementation of Interpolation Technique for Symbol Timing Recovery
in DVB-T Transceiver Design,” Proceedings of 6th IEEE
International Conference on Electro/Information Technology (EIT), E. Lansing,
Michigan, pp.427-431, May 2006. 118.
C.L. Wey, “Residue-to-Binary Converters for High-speed
Digital Signal Processing,” Proceedings of 6th IEEE International
Conference on Electro/Information Technology (EIT), E. Lansing, Michigan,
pp.421-426, May 2006. 119.
T.-H. Tsai, Y.-T. Wang, J.-H. Hung, and C.L. Wey,
“Compressed Domain Content-based Retrieval of MP3 Audio Example Using
Quantization Tree Indexing and Melody-line Tracking Method,” Proc. of IEEE
International Symp. on Circuits and Systems, 120.
C.-S. Huang and C.L. Wey, “Reliability Enhancement of CMOS
PLLs,” Proc. of the 17th
VLSI Design/CAD Symposium, 121.
C.L. Wey,
“Efficient Rectlinear Steiner Tree Construction with Rectangular Obstacels,”
Proc. of the WSEAS International Conference on Circuits, Systems,
Electronics, Control & Signal Processing (CSECS ’06), Dallas,, Texas,
November 2006. 122.
C.L. Wey and
C.-S. Huang, “Design of Reliable CMOS Phase Locked Loops,” Proc. of the 13th
IEEE International Conference on Electronics, Circuits and Systems, Nice, 123.
C.L. Wey, S.-Y.
Lin, T.-H. Tsai, and M.T. Shiue, “Efficient Implementation of Interpolation
Technique for
Symbol Timing Recovery,”
Proc. of the WSEAS International Conference on Circuits, Systems, Signal and
Telecommunication (CISST ’07), Gold Coast, 124.
C.L. Wey,
W.-C. Tang, and S-Y. Lin, “Efficient Memory-based FFT Architectures for
Digital Video Broadcasting (DVB-T/H)” VLSI-DAT, 125.
C.L. Wey and
S.-Y. Lin, “A Pipelined Divider with a Small Lookup Table,” Proc. of 7thWSEAS
International Conference on Instrumentation, Measurement, Circuits and
Systems (IMCS ’07), 126.
C.L. Wey,
W.-C. Tang, and S-Y. Lin, “Efficient VLSI Implementation of Memory-Based FFT
Processors for DVB-T Applications,” Proc. IEEE Computer Society Annual
Symposium on VLSI (ISVLSI), 127.
C.L. Wey, S.-Y. Lin, and W.-C. Tang, “Efficient Memory-Based
FFT Processors for OFDM Applications” Proc. of the 7th IEEE
International Conference on Electro/Information Technology (EIT), 128.
C.L. Wey and S.-Y. Lin, “VLSI Implementation of
Residue-to-Binary Converters for Digital Signal Processing” Proc. of the 7th
IEEE International Conference on Electro/Information Technology (EIT), 129.
S.-Y. Lin, W.-C. Tang, M.-T. Shiue,
and C.L. Wey, “High-speed, low-cost Parallel Memory-based FFT Processor for
OFDM Applications,” Proc. of
the 18th VLSI Design/CAD Symposium, 130.
C.-K. Liau, S.-Y. Lin, T.-H. Tsai,
and C.L. Wey, “A Partially Parallel Low-density Parity Check Code Decoder
with Reduced Memory for Long Code-length,” Proc. of the 18th VLSI Design/CAD
Symposium, 131.
Y.-X.
Yang, J.-F. Li, H.-N. Liu, and C.L. Wey, “Design of Cost-Efficient
Memory-Based FFT Processors Using Single-port Memories,” Proc. Of IEEE
International SOC Conference, 132. C.L. Wey and S.-Y. Lin , “High-speed, Low
Cost Parallel Memory-based FFT Processors for OFDM Applications,” Proc. IEEE
International Conference on Electronics, Circuits, and Systems, 133. C.-M. Huang, C.-M. Wu., C.-C. Yang, and
C.L. Wey, “PrSoC: Programmable System-on-Chip (SoC) for Silicon Prototyping,”
Proc. IEEE International Symp. on Circuits and Systems, 134. P.-W. Luo, J.-E. Chen, C.L. Wey, C.-H. Su,
H.-C. Liang, Y.-F. Huang, and W.-C. Wu, “On the Dedelopment of Spatial
Correlation Analysis for Yield Ehancement of Mixed-signal Integrated
Circuits,” Proc. European Test Symp., 135. C.-M. Huang, C.-M. Wu, C.-C. Yang, K.-J.
Lee, and C.L. Wey, ”Programmable System-on-Chip (SoC) for Silcion
Prototyping,” Proc. International
Symp. on Industrial Electronics, 136. S.-Y. Lin and C.L. Wey, “A Low-Cost
Continuous-flow FFT Processor for UWB Applications,” Proc. of the 19th
VLSI Design/CAD Symposium, 137. C.-W. Lin, C.-H. Su, and C.L. Wey, “A
Cascaded Sigma-Delta Modulator with DAC Error Cancellation Scheme,” Proc. of
the 19th VLSI Design/CAD Symposium, 138. C.L. Wey, S.-Y. Lin, H.-S. Wang, and C.-M.
Huang, “A Low-Cost Continuous-Flow FFT Processor for Ultra-Wideband
Applications,” Proc. of the International Conference on Advances in
Electronics and Micro-electronics (ENICS 2008), Valencia, Spain, Septemner
2008. 139. W.-C. Tsai, M.-D. Shieh, W.-C. Lin, and
C.L. Wey, “Design of Square Generator with Small Look-up Table," Proc.
of IEEE Asia Pacific Conference on Circuits and Systems, 140. C.L. Wey and S.-Y. Lin, “A Low-Cost
Continuous Flow Parallel Memory-based FFT Processor for Ultra-wideband (UWB)
Applications," Proc. of IEEE Asia Pacific Conference on Circuits and
Systems, 141. T.-H. Chien, C.-S., Lin, Y.-Z. Juang,
C.-M. Huang, and C.L. Wey, “An Edge Missing Compensator for Fast Settling
Wide Locking Range Phase-locked Loops, “ IEEE International Solid-State
Circuits Conference (ISSCC), San Francisco, CA, Feb. 2009. 142. P.-W. Luo, J.-E.
Chen, and C.L. Wey, “Yield
Evaluation of Analog Placement with Arbitrary Capacitor Ratio,” Proc.
International Symp. on Quality Electronic Design (ISQED 2009), 143. C.-M. Huang, C.-M. Wu, C.-C. Yang, S.-L.
Chen, and C.L. Wey, “Implementation and Prototyping of a Complex
Multi-project System-on-a-Chip,” Proc. International Symp. on Circuits and
Systems, 144. J.-J. Wu and C.L. Wey, “A Partially
Parallel Low-density Parity Check Code Decoder,” Proc. Electronic Technology
Symposium, 145.
C.-C.
Yang, C.-M.Huang, C.-M. Wu, W.-D. Chien, S.-L. Chen, C.-S. Chen, J.-J. Wang, and C.L.
Wey, “A Fully Configurable and Modulized Platform for
Multi-project SoC Design,” Proc. Electronic Technology Symposium, 146. K.-L. Leu﹐Y.-Y. Chen, C.-L. Wey, and J.-E. Chen, “Robustness Investigation of the
FlexRay System,” Proc. IEEE Symposium on Industrial
Embedded Systems, 147. H.-W. Huang, C.L. Wey, and J.E. Chen,
“Tango-RM: An Enhanced Switches Scheme of Resistor-string Successive
Reference Generator,” Proc. VLSI Test Technology Workshop (VTTW), 148. C.-M. Huang, Y.-T. Chang, J.-Y. Hsieh,
C.-M. Wu, C.-Y. Lin, H.-T. Wu, W.-D. Chien, J.-J. Wang, and C.L. Wey,
“MORFPGA: A Modularized FPGA Development Platform for IC Design Education and
Contests,” Proc. International Conference on Engineering Education &
Research (iCEER), pp.66-72, 149.
T.-H. Chien, C.-S. Lin, C.L. Wey, Y.-Z. Juang, and
C.-M. Huang, “High-speed and Low-power Programmable Frequency Divider,” Proc.
International Symp. On Circuits and Systems, 150.
C.-S. Lin, T.-H. Chien, and C.L. Wey, “An Effective
Phase Detector for Phase-locked Loops with 151. K.-L. Leu, Y.-Y. Chen, C.L. Wey, J.-E.
Chen, and C.-H. Huang, “A Bayesian Network Reliability Modeling for FlexRay
Systems,” Proc. International Conference on Information and Communication
Technologies (ICICT 2010), 152. K.-L. Leu, Y.-Y. Chen, C.L. Wey, and J.-E.
Chen, “A Verfication Flow for FlexRay Communication robustness Compliant with
IEC 61508,” Proc. IEEE 2nd International Conference on Industria;
Mechatronics and Automation (ICIMA 2010), 153. F.-C. Liu, Y.-J. Hsieh, Y.-J., C.-C. Wang,
and C.L. Wey, “A Nonlinear Lithium Battery Model for Charging and
Discharging,” Proc. of 2010 Electronic Technology Symposium, 154.
K.-L.
Leu, Y.-Y. Chen, C.L. Wey, and J.-E. Chen, “RobustnessAnalysis of the FlexRay
System through Fault Tree Analysis,” Proc. IEEE International Conference on
Vehicular Electronics and Safety (ICVES 2010), 155.
T.-H.
Chien, C.-S. Lin, and C.L. Wey, “A Forward Phase Detector for GSampls/s
Phase-locked Loops,” Proc. of the International Conference on Advances in
Electronics and Micro-electronics (ENICS 2010), 156. K.-C. Yang, Y.-T., Chang, C.-M. Wu, C.-M.
Huang, C.-T. Kuo, and C.L. Wey, “Case Study: An Universal Study Platform for
ESW Education,” Proc. of the International Conference on Engineering
Education & Research (iCEER), 157. C.M. Huang, C.-M. Wu, Y.-T. Chang, C.-Y.
Chen, Y.-S. Lin, C.-T. Kuo, T.-C. Liu, and C.L. Wey, “MorFPGA: A Modularized
FPGA-based Embedded System Development Platform,“ Proc. of VLSI/CAD
Symposium, 158. Y.-T. Chang, C.M. Huang, C.-M. Wu, C.-Y.
Chen, Y.-S. Lin, C.-T. Kuo, C.L. Wey, and T.-C. Liu, “MorFPGA: A Modularized
FPGA-based Embedded System Development Platform,“ Proc. of the 16th
workshop on Synthesis and System Integration of Mixed Information Technology
(SASIMI 2010), Taipei, Taiwan, Oct. 2010. 159. C.-C. Yang,
C.-Y. Lin, H.-M. Lin, Y.-C. Shih, H.-T. Wu, S.-L. Chen, T.-C. Wang, C.-M. Wu, C.M. Huang, and C.L. Wey, “ 160. C.M. Huang, C.-M. Wu, Y.-T. Chang, C.-Y.
Chen, Y.-S. Lin, C.-T. Kuo, T.-C. Liu, and C.L. Wey, “A Modularized
FPGA-Based Embedded System Development Platform,“ Proc. of the 36th
Annual Conference of the IEEE Industrial Electronics Society (IECON-2010),
Phoenix, Arizona, November 2010. 161. C.L. Wey, “A Modularized FPGA Development
Platform,” Proc. of the 12th Cross-Strait Information Technology
Conference (CSIT2010), 162. C.L. Wey, “Design for Stressability of
Analog CMOS Circuits for Gate-Oxide Reliability Enhancement,” 60th
IFIP WG Workshop, 163. C.-C. Huang, J.-E. Chen, P.-W. Luo, and
C.L. Wey, “A Fast Interconnection Capacitance Estimation in Capacitor Array
Block,” . VLSI Test Technology Workshop (VTTW), Nantou, Taiwan, July 2011. 164.
C.L. Wey, K.-C Chang, C.-H. Hsu, F.-C. Liu, and S.-W. Chen,
“Lithium Battery Models for Battery Charging and System Loading,” Proc. of
IEEE International 165.
C.-Hsu,
K.-C. Chang, C. Ouyang, K.-Y. Liao, and C.L. Wey,
“On the Implementation of CAN Buses to Battery Management Systems” Proc. of
IEEE International 166. C.-C. Huang, J.-E. Chen, P.-W. Luo, and
C.L. Wey, “Yield-aware Placement Optimization for Switched-capacitor Analog
Integrated Circuits,” Proc. of 24th IEEE International SoC
Conference (SOCC 2011), 167. C.L. Wey, K.-C. Chang, C.-I. Chiu, C.-H.
Hsu, and G.-N. Sung, “Design of Ultra-Wide-Load, 168. P.-C. Jui and C.L. Wey, “Collaboration between Academia and Technology
Research Institutes in Taiwan,” Proc. of European Workshop on Microelectronics Education
(EWME), Grenoble, France, May 2012. 169. P.-C. Jui, G.-N. Sung, and C.L. Wey,
“Efficient Algorithm and Hardware Implementation of 3N for Arithmetic and for
Radix-8 Encodings,” Proc. of IEEE Midwest Symp. on Circuits and Systems,
Boise, Idaho, Auguster, 2012. 170. S.-K. Chang and C.L. Wey, “A Fast 64-bit
Hybrid Adder Design in 90nm CMOS Process,” Proc. of IEEE Midwest Symp. on
Circuits and Systems, Boise, Idaho, Auguster, 2012. 171. CL. Wey, Z.-Y. Li, K.-C. Chang, G.-N.
Sung, and D.K. Wey, “A Fast Hysteretic Buck Converter with Adaptive Ripple
Controller,” Proc. of IEEE Midwest Symp. on Circuits and Systems, Boise,
Idaho, Auguster, 2012. 172. P.-W. Luo, T. Wang, C.L. Wey, L.-C. Cheng,
B.-L. Sheuu, and Y. Shi, “Reliable Power Delivery System Design for
Three-Dimensional Integrated Circuits,” Proc. of IEEE Computer Scieity Annual
Symp. on VLSI (ISVLSI), August, 2012. (Invited Paper). |
|
Tutorial/Short
Course Lecturer ·
“Mixed-Signal IC Design,”
Semina Series (6 hours), Workshop on Mixed-signal IC Design, National Science
Council/National Tamkang University,
July 2001. ·
“Mixed-Signal IC Testing”,
Niational Science Council, ·
"Design and Test of
Analog/Mixed-Signal Integrated Circuits," International Conference
on Chip Technology, ·
"Design, Testing, and
Fault Diagnosis of Analog/Mixed-Signal Integrated Circuits,"
Mixed-Signal Products, Semiconductor Group, Texas Instrument Inc., Dallas,
Texas, July 1997. ·
"Mixed-Signal Fault
Models and Design-for-Test", IEEE Asian Test Symp., ·
"Mixed-Signal Testing
-- a Review," IEEE International Conference on Electronics,
Circuits, and Systems, ·
"Technology for
Integrated Circuit (IC) Design and Fabrication", ·
"Some Issues on
Technology Mapping for Standard Cells in Logic Synthesis,"4th
VLSI/CAD Workshop, ·
"Design and Test of
Current-Mode Signal Processing Circuits for Sensor Array Implementation,"
·
"Analog IC Design and
Synthesis," 1992 Workshop on VLSI Designs, ·
"Synthesis and Design
of Asynchronous Sequential Circuits and Systems," ·
"Built-In Self-Test
Design of Analog and Digital Circuits," 1990 Workshop on VLSI
Testing, National Chiao-Tung University, ·
"Tutorial on
Synthesis for Testability,"Workshop on Synthesis and Testability, ·
"Tutorial on Logic
Synthesis," Workshop on Synthesis and Testability, ·
"Tutorial on
Synthesis for Testability", 2nd Workshop on CAD for VLSI, ·
"Fault-tolerant VLSI
Array Structures," Workshop on Fault-tolerant Computing,
Microelectronics and |
|
計畫名稱 |
計畫內 擔任的 工作 |
起訖年月 |
委託單位 |
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植基於直流電力線控制網路之智慧型電池管理晶片/系統之研製 |
總計畫 主持人 |
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國科會(國家型科技計畫) |
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智慧型電源管理系統模擬平台及控制網路系統之建構 |
主持人 |
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國科會(國家型科技計畫) |
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智慧型電池管理系統之研製 |
主持人 |
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財團法人金屬研究中心 |
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晶片設計實作計劃 |
總計畫 主持人 |
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國科會 |
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高安全控制網路通訊平台技術開發計劃 |
總計畫 主持人 |
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經濟部技術處學研案 |
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智慧型動態平衡電池組充電技術與系統研製計畫 |
主持人 |
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經濟部技術處學研案 |
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植基於DVB-T/H 之前瞻性車用無線視訊會議傳收機系統晶片之快速演算法與可測試硬體實現 |
主持人 |
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國科會(國家型科技計畫) |
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晶片設計實作計劃 |
總計畫 主持人 |
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國科會 |
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植基於DVB-T/H規格之前瞻性車用無線視訊會議系統傳收機系統晶片之研製 |
總計畫 主持人 |
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國科會(國家型科技計畫) |
|
植基於DVB-T/H 之前瞻性車用無線視訊會議傳收機系統晶片之快速演算法與可測試硬體實現 |
主持人 |
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國科會(國家型科技計畫) |
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晶片設計實作計劃 |
總計畫 主持人 |
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國科會 |
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植基於DVB-T/H規格之前瞻性車用無線視訊會議系統傳收機系統晶片之研製 |
總計畫 主持人 |
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國科會(國家型科技計畫) |
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前瞻控制網路技術研究與開發線傳行控系統 |
總計畫 主持人 |
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行政院科發SRB |
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晶片設計實作計劃 |
總計畫 主持人 |
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國科會 |
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線傳行控系統前瞻技術研發計畫 |
主持人 |
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中科院 |
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數位視訊廣播接收器設計 |
總計畫 主持人 |
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義隆電子 |
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數位電視廣播接收器之設計與業界延伸合作 |
總計畫 主持人 |
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教育部 |
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16th
Symposium on VLSI/CAD |
主持人 |
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教育部 |
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16th
Symposium on VLSI/CAD |
主持人 |
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國科會 |
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在無線行動及數位可操弄科技的學習情境中建立學習同伴(96-2524-S-008-001-) |
共同 主持人 |
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國科會 |
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以系統晶片技術實現數位視訊廣播接收器並建立其設計平台－子計畫七：數位電視廣播接收器之測試與內建量測技術 (95-2220-E-008-007- ) |
主持人 |
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國科會(國家型科技計畫) |
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以系統晶片技術實現數位視訊廣播接收器並建立其設計平台－總計畫 (95-2220-E-008-001- ) |
總計畫 主持人 |
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國科會 (國家型科技計畫 |
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混合訊號/類比CMOS積體電路可靠性的增強(94-2213-E-008-004-) |
主持人 |
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國科會 |
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Pattents (專利) ( 1.
魏慶隆﹐黃俊銘﹐吳建明﹐楊智喬﹐錢偉德,“具客製化介面之系統晶片載體結構,”發明專利﹐台灣,第 I
355055 號。(專利權期間：12/21/2011-10/8/2028) 2. 魏慶隆﹐黃俊銘﹐莊英宗﹐簡廷旭﹐林棋勝,“訊號邊緣遺失偵測器結構,” 發明專利﹐台灣(審核中), 98114399﹐(申請日期﹕ 3. 魏慶隆﹐黃俊銘﹐莊英宗﹐林棋勝﹐簡廷旭,“具有全除數範圍之除頻器結構,” 發明專利﹐台灣(審核中), 98119306﹐(申請日期﹕ 4. 黃俊銘﹐魏慶隆﹐吳建明﹐楊智喬﹐陳世綸﹐陳麒旭﹐林棋勝,“多層系統晶片模組結構,”發明專利﹐台灣(審核中)﹐98136383﹐(申請日期﹕ 5. 魏慶隆﹐黃俊銘﹐陳麒旭﹐吳建明﹐楊智喬﹐陳世綸﹐林棋勝,“系統晶片模組之製造方法,”發明專利﹐台灣(審核中)﹐98121088﹐(申請日期﹕ 6. 廖信豪﹐蔡瀚輝﹐曾聖翔﹐莊英宗﹐邱進峰﹐魏慶隆,“整合場效電晶體及微機電之單晶片製造方法,”發明專利﹐台灣(審核中)﹐98139061﹐(申請日期﹕ 7. 林建甫﹐蔡瀚輝﹐莊英宗﹐邱進峰﹐魏慶隆﹐“氫離子感測場效電晶體及其製造方法,”發明專利﹐台灣(審核中)﹐99100444﹐(申請日期﹕ 8. 魏慶隆、黃俊銘、陳世綸、林棋勝、簡廷旭、王建鎮,“單元化充放電之電源管理系統及其可程式化電池管理模組﹐”發明專利﹐台灣(審核中)﹐99101698﹐(申請日期﹕ 9. 黃俊銘、魏慶隆、吳建明、楊智喬、陳世綸、陳麒旭、林棋勝,“多基板晶片模組之三維系統晶片結構﹐”發明專利﹐台灣(審核中)﹐99102491﹐(申請日期﹕ 10. 黃俊銘、魏慶隆、吳建明、錢偉德、蔡維昌、張育蒼﹐“虛擬光碟櫃裝置﹐”發明專利﹐台灣(審核中), 99115044, (申請日期﹕ 11. 黃俊銘、魏慶隆、林慧敏、吳建明、楊凱超、張育蒼,“周邊虛擬化硬體平台系統,”發明專利﹐台灣(審核中)﹐99136010 (申請日期﹕ 12. 羅珮文, 陳竹一, 魏慶隆, 鄭良加, 陳繼展, 吳文慶“運用空間相關性的混合電路之良率評估器,”發明專利﹐台灣(審核中) 13. 薛木添,饒敬國﹐龍緒祥,魏慶隆﹐“基於離散哈特利轉換的正交分頻多工傳送機架構與接收機架構﹐”發明專利﹐台灣(審核中)﹐098139444 (US Patents) 1.
“Carrier
Structure of SoC with Custom Interface,” US Patent,
7,755,177 B2 ( 2.
“Edge-missing
Detector Structure,” US Patent No. 7,859,313 B2 ( 3.
“Programmable
Frequency Divider with Full Dividing Range,” US Patent No. 12/495,107 (Filed:
4.
“Fabrication method for System-on-chip (SoC) modules,” US Patent No. 12/570,049, (Filed: 5.
“Multi Layer System Chip
Module Architectures,” US Patent No. 12/685,723, (Filed: 6.
“Method for Manufacturing 3-axial Sensing MEMS Device
on Compatible CMOS Platform,” US Patent No. 12/652,068, (Filed: 7.
“Hydrogen Ion Sensitive Field Effect Transistor and
Manufacturing Method Therefore,” US Patent No. 12/724,435, (Filed: 8.
“Unitized Charging and Discharging Battery Management System and
Programmable Battery Management Module Therefore,” US Patent No. 12/728,288, (Filed: 9.
“Three-Dimensional
SoC Structure Stacking By Multiple Chip Modules,” US
Patent No. 12/752,345, (Filed: 10. “Virtual Optical Storage Device,” US Patent, No. 12/728,288
(Pending) (Filed: 11. “Virtualized Peripheral Hardware
Platform System,” US Patent, No. 12/961,783 (Pending)
(Filed: 12. “Yield Evaluator of
Mixed-Signal Circuit Using Spatial Correlation Analysis,” |