CAD for VLSI, Fall 2006
ANNOUNCEMENT
- Please move to new site about this course.
- The course at Oct. 17 (Wed) is cancelled.
INSTRUCTOR: Chien-Nan Liu
TEACHING ASSISTANT
COURSE SCHEDULE
- Introduction to electronic design automation (6 hrs)
- Binary decision diagram (3 hrs)
- Logic Synthesis (9 hrs)
- Functional Verification (6 hrs)
- Physical design (15 hrs)
- Partitioning
- Floorplanning
- Placement
- Routing
- Memory Compiler (3 hrs)
- Simulation (6 hrs)
LECTURE NOTES
- Syllabus (Sep. 8, 2006)
- Supplement to BDD (Sep. 8, 2006)
- Supplement to Functional Verification
(Sep. 8, 2006)
- Mail me to ask for other PDF files if you are the students of this course.
HOMEWORKS
PROJECTS
(Deadline: Jan. 12, 2007)
OTHER INFORMATION
EDA Summer Camp
IC/CAD Contest
For any questions, send e-mails to
jimmy@ee.ncu.edu.tw
Last modified: Jan. 4, 2007