CAD for VLSI, Spring 2007
ANNOUNCEMENT
INSTRUCTOR: Chien-Nan Liu
TEACHING ASSISTANT
COURSE SCHEDULE
- Introduction to electronic design automation (6 hrs)
- Logic Synthesis (6 hrs)
- Logic Simulation (3 hrs)
- Physical design (15 hrs)
- Partitioning
- Floorplanning
- Placement
- Routing
- High-level power/current estimation (3 hrs)
- Behavioral modeling for mixed-signal circuits (3 hrs)
- Noise-aware physical design (3 hrs)
- Project presentation (6 hrs)
LECTURE NOTES
- Syllabus (Feb. 12, 2007)
- Supplement to Logic Simulation (Feb. 12, 2007)
- Mail me to ask for other PDF files if you are the students of this course.
HOMEWORKS
PROJECTS
- Survey CAD-related paper"s"
- Each team can have 2 students
- Topics are limited on the materials mentioned in class
- Please focus on new papers only (within 5 years)
- The final report should include:
- Brief introduction about the papers you read
- Advantages and disadvantages of those methods
- Your thinking about this topic and possible improvements
- You can also attend
MOE CAD contest to be the final project
- Oral presentation is also required for each team
- Each team member should attend the oral presentation
OTHER INFORMATION
IC/CAD Contest
For any questions, send e-mails to
jimmy@ee.ncu.edu.tw
Last modified: May 14, 2007