CAD for VLSI, Spring 2008
- The final score has been posted at my office (E1-351).
Please come to check it before June 25.
INSTRUCTOR: Chien-Nan Liu
- Introduction to electronic design automation (6 hrs)
- Logic Synthesis (6 hrs)
- Logic Simulation (3 hrs)
- Physical design (15 hrs)
- High-level power/current estimation (3 hrs)
- Behavioral modeling for mixed-signal circuits (3 hrs)
- Noise-aware physical design (3 hrs)
- Project presentation (6 hrs)
- Syllabus (Feb. 19, 2008)
- Supplement to Logic Simulation (Feb. 19, 2008)
- Mail me to ask for other PDF files if you are the students of this course.
- Survey CAD-related paper"s"
- Each team can have up to 2 students
- Topics are limited on the materials mentioned in class
- Please focus on new papers only (within 5 years)
- The final report should include:
- Brief introduction about the papers you read
- Advantages and disadvantages of those methods
- Your thinking about this topic and possible improvements
- Deadline: June 11
- Oral presentation is also required for each team
- Each team member should attend the oral presentation
- The presentations are scheduled at May 28 and June 4
- The presentation schedule
- Please mail the member list to TA Chao-Hung Lu before May 14
For any questions, send e-mails to
Last modified: June 17, 2008