Digital System Design, Fall 2002
ANNOUNCEMENT
- Please move to new site about this course.
- (Dec. 31) The final exam is hold on Jan 7 (Tue) at E1-124.
- (Dec. 31) The course at Jan 2 (Thu) is cancelled.
- (Dec. 12) Please register your project number and group members to the
responsable TAs before Dec. 19. Maximum 20 groups are allowed
per problem according to your registration order.
- (Dec. 10) The course at Dec. 17 is canceled.
INSTRUCTOR: Chien-Nan Liu
TEACHING ASSISTANT
COURSE SCHEDULE
- Introduction to HDL-based design methodology (1 week)
- Language fundamentals -- Verilog HDL (2 weeks)
- HDL simulation with Verilog (1 week)
- Modeling combinational logic circuits (1 week)
- Modeling sequential elements (1 week)
- Modeling finite state machines (1 week)
- Modeling digital systems (2 weeks)
- Introduction to HDL synthesis (1 week)
- Language fundamentals -- VHDL (2 weeks)
- HDL simulation with VHDL (1 week)
- Modeling digital circuits using VHDL (2 weeks)
LECTURE NOTES
- Syllabus (Sep. 4, 2002)
- lecture 1 (Introduction, Sep. 11, 2002)
- lecture 2 (Verilog Overview, Sep. 5, 2002)
- lecture 3 (Model Comb. Circuits, Sep. 9, 2002)
- lecture 4 (Model Seq. Circuits, Sep. 9, 2002)
- lecture 5 (Model FSM, Sep. 10, 2002)
- lecture 6 (Model Systems, Sep. 11, 2002)
- lecture 7 (Synthesis Overview, Sep. 11, 2002)
- lecture 8 (VHDL Overview, Sep. 11, 2002)
- lecture 9 (VHDL Examples, Sep. 11, 2002)
HOMEWORKS and PROJECTS
Homework 1 (Due: Oct. 3, 2002)
Homework 2 (Due: Oct. 14, 2002)
Homework 3 (Due: Oct. 24, 2002)
Homework 4 (Due: Oct. 31, 2002)
Homework 5 (Due: Nov. 7, 2002)
Homework 6 (Due: Dec. 5, 2002)
Homework 7 (Due: Dec. 12, 2002)
Homework 8 (Due: Dec. 26, 2002)
Homework 9 (Due: Jan. 2, 2002)
Project #1 (Due: Jan. 13, 2003)
Project #2 (Due: Jan. 13, 2003)
Project #3 (Due: Jan. 13, 2003)
For any questions, send e-mails to
jimmy@ee.ncu.edu.tw
Last modified: Dec. 31, 2002