Design and Verification Methodology for SoC, Fall 2006
ANNOUNCEMENT
- Please move to new site about this course.
INSTRUCTOR: Chien-Nan Liu
TEACHING ASSISTANT
COURSE SCHEDULE
- Introduction to SoC design and verification (1 week)
- Reusable design methodology (1 week)
- Verification methodology for SoC (1 week)
- Introduction to SoC verification flow (2hrs)
- Tool supports for verification (1hr)
- System specification and modeling (3 weeks)
- Introduction to system modeling (3hrs)
- SystemC overview (6hrs)
- --< SystemC exercise >--
- Analog/mixed-signal system simulation (1 week)
- --< Verilog-A exercise >--
- Simulation-based functional verification methodology (3 weeks)
- Coverage-driven functional verification methodology (2hrs)
- Functional coverage metrics (2hrs)
- --< Coverage analysis exercise using Verification Navigator >--
- Test bench generation (2hrs)
- Static verification techniques (3 weeks)
- Binary decision diagram (BDD) (3hrs)
- HDL lint checking (2hrs)
- Formal verification (2hrs)
- Static timing analysis (STA) (2hrs)
- Power estimation techniques (3 weeks)
- Introduction (3hrs)
- Logic-level power estimation (3hrs)
- High-level power estimation (3hrs)
LECTURE NOTES
- Syllabus (Sep. 12, 2006)
- lecture 1 (Introduction, Sep. 12, 2006)
- lecture 2 (Reusable Design Methodology,
Sep. 12, 2006)
- lecture 3 (Verification Strategy,
Sep. 12, 2006)
- lecture 4 (System Modeling,
Sep. 12, 2006)
- lecture 5 (Mixed-Signal Verification,
Sep. 12, 2006)
- lecture 6 (Coverage-Driven Verification,
Sep. 12, 2006)
- lecture 7 (Binary Decision Diagram,
Sep. 12, 2006)
- lecture 8 (Static Verification Techniques,
Sep. 12, 2006)
HOMEWORKS AND PROJECTS
For any questions, send e-mails to
jimmy@ee.ncu.edu.tw
Last modified: Sep. 12, 2006