Design and Verification Methodology for SoC, Spring 2008
ANNOUNCEMENT
INSTRUCTOR: Chien-Nan Liu
TEACHING ASSISTANT
COURSE SCHEDULE
- Introduction to SoC design and verification (1 week)
- Reusable design methodology (1 week)
- Verification methodology for SoC (1 week)
- Introduction to SoC verification flow (2hrs)
- Tool supports for verification (1hr)
- System specification and modeling (3 weeks)
- Introduction to system modeling (3hrs)
- SystemC overview (6hrs)
- --< SystemC exercise >--
- Analog/mixed-signal system simulation (1 week)
- --< Verilog-A exercise >--
- Simulation-based functional verification methodology (3 weeks)
- Coverage-driven functional verification methodology (2hrs)
- Functional coverage metrics (2hrs)
- --< Coverage analysis exercise using Verification Navigator >--
- Test bench generation (2hrs)
- Assertion-based verification (3hrs)
- --< Assertion exercise >--
- Static verification techniques (3 weeks)
- Binary decision diagram (BDD) (3hrs)
- HDL lint checking (2hrs)
- Formal verification (2hrs)
- Static timing analysis (STA) (2hrs)
- Power estimation techniques (3 weeks)
- Introduction (3hrs)
- Logic-level power estimation (3hrs)
- --< Power analysis exercise using Prime Power >--
- High-level power estimation (3hrs)
LECTURE NOTES
- Syllabus (Feb. 19, 2008)
- lecture 1 (Introduction, Feb. 19, 2008)
- lecture 2 (Reusable Design Methodology,
Feb. 19, 2008)
- lecture 3 (Verification Strategy,
Feb. 19, 2008)
- lecture 4 (System Modeling,
Feb. 19, 2008)
- lecture 5 (Mixed-Signal Verification,
Feb. 19, 2008)
- lecture 6 (Coverage-Driven Verification,
Feb. 19, 2008)
- lecture 7 (Assertion-Based Verification,
May 6, 2008)
- lecture 8 (Binary Decision Diagram,
Feb. 19, 2008)
- lecture 9 (Static Verification Techniques,
Feb. 19, 2008)
- lecture 10 (Power Estimation Techniques,
Feb. 19, 2008)
HOMEWORKS AND PROJECTS
For any questions, send e-mails to
jimmy@ee.ncu.edu.tw
Last modified: May 6, 2008