中文版

描述: wey

Chin-Long Wey, Ph.D.

Professor

Department of Electrical Engineering

National Central University

Jhongli, Taoyuan, Taiwan

e-mail: clwey@ee.ncu.edu.tw

 

 

Current Positions：

Professor, Department of Electrical Engineering, National Central University

Education：

Ph.D in Electrical Engineering, Texas Tech University, Lubbock, Texas (1983)

MS in Computer Science, Texas Tech University, Lubbock, Texas (1980)

BS in Mathematics, National Central University, Jhongli, Taiwan (1973)

Professional Experience：

2007-2010

Director General

National Chip Implementation Center (CIC)

Vice President

National Applied Research Laboratories (NARL),

National Science Council (NSC), Taiwan

2003-2006

Dean

College of Electrical Engineering and Computer Science,

National Central University (NCU)

1983-2003

Professor

Department of Electrical and Computer Eng., Michigan State University (MSU), E. Lansing, Michigan, USA

2001-2002

Co-Founder & President

JMicron Technology Corp., Hsinchu, Taiwan

JMicron USA Technology Corp., Irvine, CA, USA

1999

Bosch Faculty Fellow

Robert Bosch GmbH, Reultingen, Germany

1995-1997

Founding Director

Computer Engineering Program, College of Engineering, MSU,

E. Lansing, MI, USA

 

Research：

Design and Test of Integrated Circuits (ICs), Fault-tolerant System Design, Design for Reliability and Yield.

Honors and Awards

1.            IEEE Fellow Evaluation Committee (Computer Science Society, CSS), 2011

2.            IEEE Fellow Evaluation Committee (Circuits and Systems Society, CASS), 2011

3.            IEEE Fellow, 2011

4.            Recipient of Silver Metal of 2011 Taipei International Invention Show & Technomart Invention Contest for the Invention Patent “Unitized Charging and Discharging Battery Management System and Programmable Battery Management Module Therefore,” 2011

5.            Recipient of the Award for Outstanding Contributions in Science and Technology, National Applied Research Laboratories (2010)

6.            Recipient of the Award for Outstanding Contributions in Science and Technology, National Applied Research Laboratories (2009)

7.            Distinguished Research Fellow, National Applied Research Laboratories (2007~2010)

8.            TSMC Distinguished Chair Professor, National Central University (2004, 2007)

9.            NSC Chair Professor, Department of Electronics Engineering, National Yunlin University of Science and Technology (2003)

10.         Distinguished Speaker Award, Taiwanese Engineers and Scientists Society of America, CA, USA (2003).

Current Research Projects

1.            Integrated Battery Charger IC and System Design

2.            Fault-tolerant Design of Integrated Systems with FlexRay.

3.            Design for X-ability.

 

 

Project Titles (2006~)

Position

Duration

Funding Agent

Smart Battery Management Integrated Circuits/Systems on DC Power-Line Control Bus

PI

5/2011-7/2014

NPIE , NSC

High Speed and Robust Central Communication Protocol for Electrical Vehicle

PI

5/2011-7/2014

NPIE , NSC

Chip Implementation of Smart Battery Management System

Co-PI

1/2011-12/2011

MIRDC

The Network Communication Technology for Safety-Critical Control Systems

PI

6/2009-5/2010

DOIT, MOEA

Development of Smart Battery Management Systems

Co-PI

6/2009-5/2010

DOIT, MOEA

MIMO Transceiver SOC Design for DVB-T/H-based Mobile Video Conference System

PI

8/2007-7/2010

NSOC , NSC

Research on Advanced Networks for X-by-Wire Systems

PI

7/2006-12/2006

CSIST

Design of Digital Video Broadcasting, DVB-T, Transceiver

PI

8/2006-7/2007

Elan Microele.Corp

NSC: National Science Council; NPIE: National Program of Smart Electronics; NSOC: National Program of System-on-a-Chip;

MIRDC: Metal Industrial Research & Development Center; CSIST: Chung-Shan Institute of Science and Technology

MOEA: Ministry of Economic Affairs;  DOIT: Department of Industrial Technology;

 

List of Publication

Book Chapters

1.        C.L. Wey, C.-c. Wu, and R. Saeks, "Analog Fault Diagnosis," Testing and Diagnosis of VLSI and ULSI, Ed. by M. Sami and F. Lombardi, Kluwer Academic Publisher, pp.117-150, 1988.

2.        F. Lombardi and C.L. Wey, "On Front Reconfiguration of VLSI Arrays," Testing and Diagnosis of VLSI and ULSI, Ed. by M. Sami and F. Lombardi, Kluwer Academic Publisher, pp.429-468, 1988.

3.        C.L. Wey and R. Saeks, "On the Implementation of Analog ATPG: The Linear Case," Analog Fault Diagno­sis, Edited by R.W. Liu, IEEE PRESS, 1989.

4.        C.L. Wey, "A Searching Approach Self-Testing Algorithm for Analog Fault Diagnosis," Testing and Diagno­sis of Analog Circuits and Systems, Ed. by R.W. Liu, Van Nostrand Reinhold, New York, pp.147-185, 1991.

5.        C.L. Wey, "Test techniques for CMOS Switched-Current Circuits," Analog and Mixed-Signal Test, Edited by B. Vinnakota, Prentice-Hall, Inc., 1998.

  

Journal Papers

1         C.-c. Wu, K. Nakajima, C.L. Wey, and R. Saeks, "Analog Fault Diagnosis with Failure Bounds," IEEE Trans. on Circuits and Systems, Vol. CAS-29, No.5, pp.277-284, May 1982.

2         C.L. Wey and R. Saeks, "On the Implementation of Analog ATPG: The Linear Case," IEEE Trans. on Instru­mentation and Measurement, Vol. IM-34, No.3, pp.442-449, September 1985.

3        C.L. Wey, "A Decision Process for Analog System Fault Diagnosis," IEEE Trans. on Circuits and Systems, Vol. CAS-34, No.1, pp.107-109, January 1987.

4        C.L. Wey, M.K. Vai, and F. Lombardi, "On the Design of a Redundant PLA," IEEE Journal of Solid-State Circuits. Vol. SC-22, No.1, pp.114-117, February 1987.

5        C.L. Wey and F. Lombardi, "On the Repair of Redundant RAM’s," IEEE Trans. on CAD of Integrated Cir­cuits and Systems. Vol. CAD-6, No.2, pp.222-231. March, 1987.

6        C.L. Wey and F. Lombardi, "On the Novel Self-test Approach to Digital Test," The Journal of Computers, Vol.30, No.3, pp.258-267, March 1987.

7        C.L. Wey, "Design of Testability for Analog Fault Diagnosis," International Journal of Circuit Theory and Application, Vol.15, No.2, pp.123-142, April 1987.

8        F. Lombardi and C.L. Wey, "Algorithms for Functional Testing of Digital Systems," (Invited Paper) Interna­tional Journal of Electronics, Vol.62, No.5, pp.707-732, May 1987.

9        B.L. Jiang, C.L. Wey, and L.J Fan, "Fault Prediction for Analog Circuits," Journal of Circuits, Systems, and Signal Process. Vol.7, No.1, pp.95-109, January 1988.

10     S.-W. Chan and C.L. Wey, "The Design of Concurrent Error Diagnosable Systolic Arrays for Band-Matrix Multiplication," IEEE Trans. on CAD of Integrated Circuits and Systems (Special issue on Testable and Maintainable Design), Vol. CAD-7, No.1, pp.21-37, January 1988.

11     S.-W. Chan, S.S. Leung, and C.L. Wey, "A Systematic Design Strategy for Concurrent Error Diagnosable It­erative Logic Arrays," IEE Proceedings, Part E, Computers and Digital Techniques, Vol.135, No.2, pp.87- 94, March 1988.

12     C.L. Wey, "On Yield Considerations for the Design of Redundant Programmable Logic Arrays," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. CAD-7, No.4, pp.528-535, April 1988.

13     C.L. Wey and R. Saeks, "On the Implementation of Analog ATPG: The Nonlinear Case," IEEE Trans. on In­strumentation and Measurement, Vol. IM-37, No.2, pp.252-258. June 1988.

14     C.L. Wey, "Parallel Processing for Analog Fault Diagnosis," International Journal of Circuit Theory and Ap­plication, Vol.16, pp.303-316, July 1988.

15     B.L. Jiang, and C.L. Wey, "Fault Prediction Process for Large Analog Circuit Networks," International Jour­nal of Circuit Theory and Applications. Vol.17, No.2, pp.141-149, April 1989.

16     C.L. Wey and S.M. Chang, "Test Generation for C-testable Array Dividers," IEE Proceedings, Part E, Com­puters and Digital Techniques, Vol.136, No.5, pp.434-442, September 1989.

17     T.Y. Chang and C. L. Wey, "Design of fault diagnosable and repairable PLA," IEEE Journal of Solid-State Circuits. Vol. SC-24, No.5, pp.1451-1454, October 1989.

18     C.L. Wey, and T.Y. Chang, "An Efficient Output Phase Assignment for PLA Minimization," IEEE Trans. on CAD of Integrated Circuits and Systems, Vol.9, No.1, pp.1-7, January 1990.

19     C.L. Wey, "Built-In Self-Test (BIST) Structure for Analog Circuits Fault Diagnosis," IEEE Trans. on Instru­mentation and Measurement. Vol. IM-39, No.2, pp.517-521, June 1990.

20     C.L. Wey and T.Y. Chang, "Design of VLSI-Based Parallel Multipliers," IEE Proceedings, Part E, Comput­ers and Digital Techniques. Vol.137, No.4, pp.328-336, July1990.

21     B.L. Jiang and C.L. Wey, "Fault Prediction for Analog Circuits - Reply," Journal of Circuits, Systems, and Signal Process. Vol.9, No.4, p.503, 1990.

22     C.L. Wey, T.Y. Chang, and J.Y. Ding, "Design of Fault Diagnosable and Repairable Folded PLAs for Yield Enhancement," IEEE Journal of Solid-State Circuits. Vol.26, No.1,pp.54-57, January 1991.

23     C.L. Wey, "Alternative Built-In Self-Test Structure (BIST) for Analog Circuit Fault Diagnosis," Electronics Letters. Vol.27, No.18, pp.1627-1628, August 1991.

24     C.L. Wey, "Concurrent Error Detection in Current-Mode A/D Converter," Electronics Letters. Vol.27, No.25, pp.2370-2372, December 1991.

25     C.L. Wey, "Concurrent Error Detection in Array Dividers by Alternating Input Data," IEE Proceedings, Part E, Computers and Digital Techniques. Vol.139, No.2, pp.123-130, March 1992.

26     C.L. Wey and S. Krishnan, "An Accurate Current-mode Divide-by-two Circuit," Electronics Letters. Vol.28, No.9, pp.820-822, April 1992.

27     C.L. Wey and S. Krishnan, "Built-In Self-Test (BIST) Structures for Analog Circuit Fault Diagnosis with Cur­rent Test Data," IEEE Trans. on Instrumentation and Measurement, Vol. IM-41, No.4, pp.535-539, August 1992.

28     C.L. Wey, S. Krishnan,, and S. Sahli, "Design of Concurrent Error Detectable Current-Mode A/D converters for Real-time Applications," Analog Integrated Circuits and Signal Processing, No.4, pp.65-74, July 1993.

29     S. Krishnan, and C.L. Wey, "An Accurate Reference-generating Circuit for Successive Approximation Current- mode A/D Converters," International Journal of Circuit Theory and Application. No.21, pp.361-369, August 1993.

30     M.-D. Shieh, C.L. Wey, and P.D. Fisher, "Fault Effects in Asynchronous Sequential Logic Circuits," IEE Pro­ceedings, Part E, Computers and Digital Techniques. Vol. 140, No.6, pp.327-332, November 1993.

31     J.-W. Kang, P.D. Fisher, and C.L. Wey, "An Efficient Modeling and Synthesis Procedure of Asynchronous Sequential Logic Circuits," IEE Proceedings, Part E, Computers and Digital Techniques. Vol.141, No.1, pp. 61-64, January 1994.

32     C.L. Wey, N. Berthlot, and B. Veltkamp, "Concurrent Error Detection in High Speed Carry-free Dividers," IEE Proceedings, Computers and Digital Techniques, Vol.141, No.6, pp.356-360, November 1994

33     C.-S. Lai and C.L. Wey, "SOLiT: An Automated system for Synthesizing Reliable Sequential Circuits with Multi-level Logic Implementation," IEE Proceedings, Computers and Digital Techniques, Vol.142, No.1, pp.49-54, January 1995.

34     R. Huang and C.L. Wey, "Simple Yet Accurate Current Copiers for Low-Voltage Current-Mode Signal Pro­cessing Applications," International Journal of Circuit Theory and Application, vol.23, pp.137-145, No.2, March 1995.

35     C.L. Wey, "Design and Test Generation of C-testable High Speed Dividers," IEE Proceedings, Computers and Digital Techniques,.Vol.142, No.3, pp.193-200, May 1995.

36     J.-W. Kang, C.L. Wey, and P.D. Fisher, "Applications of Bipartite Graphs for Race-free State Assignment," IEEE Trans. on Computers, Vol.44, No.8, pp. 1002-1011, August 1995.

37     C.L. Wey, S. Krishnan,, and S. Sahli, "Test Generation and Concurrent Error Detection in Current-Mode A/D Converters," IEEE Trans. on CAD, Vol. 14, No.10, pp. 1291-1298, October 1995.

38     R. Huang and C.L. Wey, "Simple Low-voltage, High-speed, High-linearity V-I Converter with S/H for An­alog Signal Processing Applications," IEEE Trans. on Circuits and Systems. Part II. Analog and Digital Sig­nal Processing. Vol.43, No.1, pp.52-55, January 1996.

39     C.L. Wey, "Built-in Self-test (BIST) Design of High-speed Carry-free Dividers," IEEE Trans. on VLSI Sys­tems, Vol. 4, No. 1, pp. 141-145, March 1996.

40     R. Huang and C.L. Wey, "Design of High-speed, High-accuracy Current Copiers for Low-voltage Analog Signal Processing Applications," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing. Vol.43, No.12, pp.836-839, December 1996.

41     C.L. Wey, "Built-in Self-test (BIST) Design of Current-mode Algorithmic A/D Converter," IEEE Trans. on Instrumentation and Measurement. Vol. 46, No. 3, pp.667-671, June 1997.

42     T.-H. Pan and C.L. Wey, "GRASS: an Efficient Gate Re-assignment Algorithm for Inverter Minimization in Post Technology Mapping," IEE Proceedings, Computers and Digital Techniques. Vol. 144, No.5, pp.348- 352, September 1997.

43     C.-P. Wang and C.L. Wey, "Fault Macromodel for Switches in Switched-current Circuits," International Journal of Circuit Theory and Applications. Vol. 26, pp.93-102. January 1998.

44     R. Huang and C.L. Wey, "A High-performance CMOS Oversampling Current Sample/Hold (S/H) Circuit Us­ing Feedforward Approach," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Pro­cessing, Vol. 45, No.3, pp. 395-399. March 1998.

45     W.-H. Huang, and C.L. Wey, "ATPRG: An Automatic Test Program Generator Using HDL-A for Fault Diag­nosis of Analog/Mixed-signal Integrated Circuits," IEEE Trans. on Instrumentation and Measurement., Vol. 47, No. 2, pp.426-431, April 1998.

46     W.-H. Huang and C.L. Wey, "Diagnosability Analysis of Analog Circuits," International Journal of Circuit Theory and Application. Vol. 26, No.5, pp.439-451, September 1998.

47     C.L. Wey and M.-D. Shieh, "Design of High-speed Square Generator," IEEE Trans. on Computers.  Vol.47, No. 9, pp.1021-1026, September 1998.

48     J.-S. Wang and C.L. Wey, "Design and Analysis of High Performance Current Reference Generators for Low-power CMOS Data Converters," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing. Vol.46, No.5, pp.647-652, May 1999.

49     J.-S. Wang and C.L. Wey, "A 12-bit, 100ns/b, 1.9mW CMOS Switched-current Cyclic A/D Converter," IEEE Trans. on Circuits and Systems, Part II. Analog and Digital Signal Processing, Vol.46, No.5, pp.507- 516, May 1999

50     Y. Wan and C.L. Wey, "Efficient Algorithms for Binary Logarithmic Conversion and Addition," IEE Proceedings, Computers and Digital Techniques. Vol.146, No.3, pp.168-176, May 1999.

51     C.L. Wey and C.-P. Wang, "A Fast Radix-4 SRT Divider and Its VLSI Implementation," IEE Pro­ceedings, Computers and Digital Techniques. Vol. 146, No.4, pp.205-210, July 1999.

52     C.L. Wey and W.-H. Huang, "Designability Check for Analog Circuits with Incomplete Implementation In­formation," IEEE Trans. on Circuits and Systems, Part I, Fundamental Theory and Applications. Vol. 46, No.8, pp.939-949, August 1999.

53     Y. Wan, M.A. Khalil, and C.L. Wey, "Efficient Conversion Algorithms for Long-word-length Binary Log­rithmic Numbers and Hardware Implementation," IEE Proceedings, Computers and Digital Techniques. Vol. 146, No.6, pp.295-301, November 1999.

54     R. Huang, J.-S. Wang, and C.L. Wey, "A Fully Differntial Current Copier for Performance Improvement," In­ternational Journal of Circuit Theory and Application. Vol. 28, No.2, pp. 101-108, March 2000.

55     C.-P. Wang and C.L. Wey, "Design of High performance Current Comparator as Built-in Testers of CMOS Switched-current  Circuits," International Journal of Analog Integrated Circuits and Signal Processing, Vol.23, No.3, pp.179-188, June 2000.

56     C.L. Wey, "Design of Fast High-radix SRT Dividers and Their VLSI Implementation," IEE Proceedings, Computers and Digital Techniques, Vol.147, No.4, pp.275-282, July 2000.

57     C.L. Wey, “ReSTRO: Efficient Rectlinear Steiner Tree Construction with Rectangular Obstacles,” WSEAS Trans. on Circuits and Systems, Vol.5, pp.1768-1774, December 2006.

58     C.L. Wey, S.-Y. Lin, T.-H. Tsai, and M.T. Shiue, “Efficient Implementation of Interpolation Technique for Symbol Timing Recovery in DVB-T Transceiver Design,” WSEAS Trans. on Circuits and Systems, Vol. 6, pp.215-221, January 2007.

59     C.L. Wey and S.-Y. Lin, “An Efficient Pipelined Divider with a Small Lookup Table,” WSEAS Trans. on Electronics, Vol. 4, pp.56-52, March 2007.

60     C.L. Wey, C.-S. Huang, and S. Quan, “Design of Reliable CMOS Phase Locked Loops,” International Journal of Electrical Engineering, Vol.14, No.3, pp.195-206, 2007.

61     P.-W. Luo, J.-E. Chen, C.L. Wey, L.-C. Cheng, J.-J. Chen, and W.-C. Wu, “Impact of Capacitance Correlation on Yield Enhancement of Mixed-signal/Analog Integrated Circuits,” IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 27, No.11, pp.2097-2101, November 2008.

62     P.-W. Luo, J.-E. Chen, and C.L. Wey, “Yield Evaluator of Mixed-Signal Circuit Using Spatial Correlation Analysis,” SoC Technical Journal, Vol. 9, pp. 87-95, December 2008.

63     C.L. Wey, M.-D. Shieh, and S.-Y. Lin, “Efficient Algorithm and Hardware Implementation of Finding First Two Minimum Values for LDPC Decoding Applications,” IEEE Trans. on Cicuits and Systems I, Vol. 55, pp.3430-3437, December 2008.

64     C.-S. Lin, T.-H. Chien, C.L. Wey, C.-M. Huang, and Y.-Z. Juang, “An Edge Missing Compensator for Fast Settling Locked Range Phase-locked Loops,” IEEE Journal of Solid-State Circuits, Vol.44, No.11, pp.3102-3110, November 2009.

65      J.-E. Chen, P.-W. Luo, and C.L. Wey, ”Placement Optimization for Yield Improvement of Switched-capacitor Analog Integrated Circuits,” IEEE Trans. on Computer CAD of Integrated Circuits and Systems, Vol.29, No.2, pp.313-318, February 2010.

66      C.-C. Wang, G.-N. Sung, P.-C., Chen, and C.L. Wey, “A Transceiver Frontend for Electronic Control Units in FlexRay-based Automotive Communication Systems,” IEEE Trans. on Circuits and Systems, I: Regular Papers, Vol. 57, No. 2, pp.460-470, February 2010.

67      C.-M. Huang, Y.-T. Chang, J.-Y. Hsieh, C.-M. Wu, H.-T. Wu, C.-Y. Lin, J.-J. Wang, and C.L. Wey, “MorFPGA: A Modularized FPGA Development Platform for IC Design Education,” Innovations 2010: World Innovations in Engineering and Research, pp.197-212, August 2010.

68      S.-Y. Lin, C.L. Wey and M.-D. Shieh, “Low-Cost FFT Processor for DVB-T2 Applications,” IEEE Trans. on Consumer Electronics, Vol.56, No.4, pp.2072-2079, November 2010.

69      C.L. Wey, S.-Y. Lin, H.-S. Wang, H.-L. Cheng, and C.-M. Huang, “A Low-cost Continuous-flow Parallel Memory-based FFT Processor for UWB Applications,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No.1, pp.315-323, January 2011.

70      P.-W. Luo, J.-E. Chen, M.-Y. Huang, and C.L. Wey, “Design Methodology for Yield Enhancement of Switched-capacitor Analog Integrated Circuits,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No.1, pp.352-361, January 2011.

71       C.-M. Huang, C.-M. Wu, C.-C. Yang, S.-L. Chen, C.-S. Chen, J.-J. Wang, K.-J. Lee, and C.L. Wey, “Programmable System-on-chip (SoC) for Silicon Prototyping,” IEEE Trans. on Industrial Electronics, Vol. 58, No.3, pp.830-838, March 2011.

72      C.L. Wey, S.-Y. Lin, P.-Y.Tsai, and M.-D. Shieh,“Reconfigurable Homogenous Multi-core FFT Processor Architectures for Hybrid SISO/MIMO OFDM Wireless,”  IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E94-A, No. 7, pp. 1530-1539, July 2011.

73      C.-M. Lu and C.L. Wey, “A Controller Design for Micro-capsule Active Matrix Electrophoretic Dsiplays,” IEEE Journal of Display Technology, Vol. 7, No. 8, pp.434-442, August 2011.

74      C.-M. Lu and C.L. Wey, “A Controller Design for Color Displays Using Electrophoretic Inks and Color Filters,” IEEE Journal of Display Technology. Vol. 7, No. 9, pp.482-489, September 2011.

75   C.-S. Lin, T.-H. Chien, and C.L. Wey, “A 5.5GHz, 1mW, Full-modulus-rang Programmable Frequency Divider in 90nm CMOS Process,” IEEE Trans. on Circuits and Systems II, Vol. 58, No.9, pp.550-554, September 2011.

76  C.-M. Lu and C.L. Wey, “A Controller Design for Micro-Cup Active Matrix Electrophoretic Displays,” Journal of the Society for Information Display, pp.103-108, February 2012

77   C.-M. Lu and C.L. Wey, “A Controller Design for High Quality Images on Micro-Capsule Active Matrix Electrophoretic Displays,” Journal of Information Display, issue 13(1), pp.21-30, March 2012.

 

 

Conference Papers

1.    C.-c. Wu, K. Nakajima, C.L. Wey, and R. Saeks, "Analog fault diagnosis with failure bounds," Proc. 24th Midwest Symp. on Circuits and Systems, Albuquerque, NM, pp.515-520, June 1981.

 2.   C.L. Wey, D. Holder, and R. Saeks, "On the Implementation of an Analog ATPG," Proc. IEEE 3rd Automatic Test Program Generation (ATPG) workshop, pp.33-36, San Francisco, CA, March, 1983.

 3. C.L. Wey, D. Holder, and R. Saeks, "On the Implementation of an Analog ATPG," Proc. IEEE international Symp. on Circuits and Systems, Newport Beach, CA, pp.1102-1105, May 1983.

 4. C.L. Wey and R. Saeks, "On the Implementation of Analog ATPG II," IEEE 4th Automatic Test Program Gen­eration (ATPG) workshop, Washington D.C., February 1984.

 5. C.L. Wey and R. Saeks, "On the Implementation of an Analog ATPG: The Nonlinear Case," Proc. IEEE In­ternational Symp. on Circuits and Systems, Montreal, Canada, pp.213-216, May 1984.

 6. C.L. Wey, "Parallel Processing for Analog Fault Diagnosis," Proc. 27th Midwest Symp. on Circuits and Sys­tems, Morgantown, WV, pp.435-438, June 1984.

 7. C.L. Wey, "UUT Modeling for Digital Test - A Self-test Approach," Proc. IEEE Fourth Annual Phoenix Con­ference on Computers and Communications, Phoenix, AZ, pp.312-316, March 1985.

 8. C.L. Wey, "Design of Testability for Analog Fault Diagnosis," Proc. IEEE International Symp. on Circuits and Systems, Kyoto, Japan, pp.515-518, June 1985.

 9. F. Lombardi and C.L. Wey, "Fault Identification Algorithm for VLSI Systems," Proc. ICCD, International Conference on Computer Design: VLSI in Computers, Port Chester, NY, pp. 693-696, October 1985.

10. F. Lombardi and C.L. Wey, "On a Multiprocessor System with Dynamic Redundancy," Proc. Real-Time Sys­tems Symposium, San Diego, CA. pp. 3-12, December 1985.

11. F. Lombardi and C.L. Wey, "Diagnosis and Fault Identification Algorithms for Large Scale Computing Sys­tems," Proc. First International Conference on Supercomputing Systems, Tarpon Spring, FL, pp. 404-413. December 1985.

12. C.L. Wey and F. Lombardi, "On a New Decision Process for t-diagnosis of an Analog System," Proc. IEEE International Symp. on Circuits and Systems, San Jose, CA, pp.1255-1256, May 1986.

13. B.L. Jiang and C.L. Wey, "Multiple Fault Diagnosis with Failure Bound for Analog Circuits," Proc. IEEE In­ternational Symp. on Circuits and Systems, San Jose, CA, pp.1261-1264, May 1986.

14.    C.L. Wey and F. Lombardi, "On the Repair of Programmable Logic Arrays," Proc. IEEE International Symp. on Circuits and Systems, San Jose, CA, pp.649-652, May 1986.

15.    C.L. Wey, T.Y. Chang, and M.K. Vai, "On the Design of Fault-Tolerant Programmable Logic Arrays," Proc. International Computer Symp., Tainan, Taiwan, pp.398-404, December 1986.

16.    C.L. Wey, "An Efficient Unrepairability Detection Scheme for Redundant RAM Test System," Proc. Interna­tional Computer Symp., Tainan, Taiwan, pp.406-413, December 1986.

17.    C.L. Wey and F. Lombardi, "Efficient, Yet Simple Algorithms for Repairing Redundant RAMs," Proc. IEEE International Symp. on Circuits and Systems, Philadelphia, PA, pp. 871-874, May 1987.

18.    C.L. Wey and F. Lombardi, "Analysis and Design of Repairable PLAs," Proc. CompEuro, pp.363-366, May 1987.

19.    C.L. Wey, "On Yield Considerations for the Design of Redundant Programmable Logic Arrays," Proc. ACM/ IEEE Design Automation Conference (DAC), pp.622-628, June 1987.

20.  B.L. Jiang and C.L. Wey, "Fault Prediction Process for Large Analog Circuit Networks," Proc. 30th Midwest Symp. on Circuits and Systems, pp. 132-135, August 1987.

21.    C.L. Wey, T.Y. Chang, and Y.F. Chen, "The Design of VLSI-based Parallel Multipliers," Proc. 30th Midwest Symp. on Circuits and Systems, pp.97-104, August 1987.

22.   S.M. Chang and C.L. Wey, "Test Generation for C-testable Array Multipliers," Proc. 25th Allerton Confer­ence, Univ. of Illinois. pp. 1040-1049, Sept. 1987

23.   C.L. Wey and T.Y. Chang, "Minimization of PLAs with Ground True Outputs," Proc. of 25th ACM/IEEE De­sign Automation Conference (DAC), Anaheim, CA. pp.421-426, June 1988.

24.   T.Y. Chang and C.L. Wey, "Design and Test of Electrically Field-Repairable APLAs," Proc. 31st Midwest Symp. on Circuits and Systems, St. Louis, MO, pp.36-39, August 1988.

25.   C.L. Wey and T.Y. Chang, "An Efficient Boolean Comparison Process for Logic Verification," Proc. 31st Midwest Symp. on Circuits and Systems, St. Louis, MO, pp.1175-1178, August 1988.

26.   C.L. Wey, B.L. Jiang, and G. Wierzba, "Built-In Self-Test for Analog Circuit Networks," Proc. 31st Midwest Symp. on Circuits and Systems, St. Louis, MO, pp.862-865, August 1988.

27.   C.L. Wey and S.-M. Chang, "Built-in Self-test (BIST) Design of C-testable Baugh-Wooley Array Multiplier," Proc. 31st Midwest Symp. on Circuits and Systems. St. Louis, MO. pp.1186-1189, August 1988.

28.   C.L. Wey and S.-M. Chang, "Test Generation of C-testable Array Dividers," Proc. IEEE International Confer­ence on Computer Design: VLSI in Computers & Processors (ICCD ’88), Port Chester, NY, pp.140-144, Oc­tober 1988.

29.   C.L. Wey, and B.L. Jiang, "Built-in Self-test (BIST) Design of Large Scale Analog Circuit Networks," Proc. 1989 IEEE International Symp. on Circuits and Systems, Portland, OR, pp.2048-2051, May 1989.

30.   C.L. Wey, S.-M. Chang, and J.-Y. Jou, "An Efficient Output Phase Assignment for MultiLevel Logic Minimi­zation," Proc. 1989 International Workshop on Logic Synthesis, North Carolina, May 1989.

31.   C.L. Wey, "Fault Location in Repairable Programmable Logic Arrays," Proc. IEEE International Test Confer­ence (ITC), Washington, D.C. pp.679-685, August 1989.

32.   C.L. Wey, S.-M. Chang, and J.-Y. Jou, "OPAM: An Efficient Output Phase Assignment for Multilevel Logic Minimization," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’89), Cambridge, MA, pp.270-273. October 1989.

33.   C.L. Wey, "Output Phase Assignment for Logic Minimization," (invited), 2nd Workshop on CAD for VLSI, Taiwan, March, 1990.

34.   C.L. Wey, J. Ding, and T.-Y. Chang, "Design of Repairable and Fully Diagnosable Folded PLAs for Yield En­hancement," Proc. 27th ACM/IEEE Design Automation Conf. (DAC), Orlando, FL, pp.327-332,  June 1990.

35.   C.L. Wey and J. Ding, "Design of Repairable and Fully Testable Folded PLAs for Yield Enhancement," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’90), Cam­bridge, MA, pp.112-115, September 1990.

36.   C.L. Wey and T.-Y. Chang, "On the Design of Concurrent Error Detectable Multiply and Divide Arrays," Proc. International Computer Symposium, Hsinchu, Taiwan, ROC, pp.564-570, December 1990.

37.   C.L. Wey, "Concurrent Error Detection in Array Dividers by Alternating Input Data," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’91), Cambridge, MA, pp.114-117, October 1991.

38.   C.L. Wey, M.-D. Shieh, and P.D. Fisher, "On Synthesis for Testability of Asynchronous Sequential Logic Cir­cuits," IFIP International Workshop on the Relationship between Synthesis, Test, and Verification. Berkeley, CA, November 1991.

39.    C.-S. Lai, and C.L. Wey, "An Efficient Algorithm for Reducing Hardware Overhead in Self-checking Circuits and Systems," Proc. 35th Midwest Symp. on Circuits and Systems, Washington, D.C., pp.1538-1541, August 1992.

40.    J.-W. Kang, C.L. Wey, and P.D. Fisher, "An Efficient Modelling and Synthesis Procedure of Asynchronous Sequential Logic Circuits," Proc. 35th Midwest Symp. on Circuits and Systems, Washington, D.C., pp.512-515, August 1992.

41.    M.-D. Shieh, C.L. Wey, and P.D. Fisher,"Model of Asynchronous Finite State Machines and Their Pipelined Structures," Proc. 35th Midwest Symp. on Circuits and Systems, Washington, D.C., pp.659-662, August 1992.

42.    S. Krishnan, S. Sahli, and C.L. Wey, "Test Generation and Concurrent Error Detection in Current-mode A/D converters," Proc. IEEE International Test Conference (ITC), Baltimore, MD., pp. 312-320, September 1992.

43.    S. Sahli, S. Krishnan, and C.L. Wey, "Design of Concurrent Error Detectable Current-Mode A/D converters," Proc. International Conference on Microelectronics, Tunisia, pp.1.1.1.1-4, December 1992.

44.    J.-W. Kang, C.L. Wey, and P.D. Fisher, "Race-free State Assignments Using Bipartite Graphs," Proc. of IEEE Symposium on Circuits and Systems, Chicago, pp.2560-2563. May 1993.

45.   M.-D. Shieh, C.L. Wey, and P.D. Fisher, "Scan Design for Asynchronous Sequential Logic Circuits Using SR-latches," Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, August 1993.

46.   J.-W. Kang, C.L. Wey, and P.D. Fisher, "A Synthesis Procedure for Large-Scale Asynchronous Finite State Machines," Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, August 1993.

47.   C.-S. Lai and C.L. Wey, "Design of Fast, Yet Low Hardware Cost Self-testing Berger Code Checkers," Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, August 1993.

48.   C.L. Wey, M.-D. Shieh, and P.D. Fisher, "ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’93), Cambridge, MA, pp. 159-162, October 1993.

49.   R. Huang and C.L., Wey, "A Simple Yet Accurate Current Copier," Proc. 37th Midwest Symp. on Circuits and Systems, Lafayette, LA, pp. 121-124, August 1994.

50.   C.L. Wey, "Design of C-testable High Speed Dividers," Proc. 37th Midwest Symp. on Circuits and Systems, Lafayette, LA, pp. 261-264, August 1994.

51.   S. Krishnan and C.L. Wey, "A Parallel Current-mode A/D Converter Array with a Common Current Refer­ence-Generating Circuit," Proc. 37th Midwest Symp. on Circuits and Systems, Lafayette, LA, pp.1168-1171, August 1994.

52.   C.L. Wey, "Concurrent Error Detection in High Speed Carry-free Dividers," Proc. IEEE International Confer­ence on Computer Design: VLSI in Computers & Processors (ICCD ’94), Cambridge, Massachusetts, pp. 124- 127, October 1994.

53.   R. Huang and C.L. Wey, "High-speed, Low-voltage V-I Converters for Analog Signal Processing Applica­tions," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS’ 94), Taipei, Taiwan, pp. 494-498, December 1994

54.   C.L. Wey, "Built-in Self-test (BIST) Design of High-speed Carry-free Dividers," Proc. IEEE Symposium on Circuits and Systems, Seattle, WA, pp.1916-1919, May 1995.

55.   C.L. Wey, A.Y. Tetelbaum, and T. Bickart, "A Performance-driven Placement Approach of Standard Cells," Proc. International Conference on Intelligent Systems, Gelengick, Russia, pp.31-35, September 1995.

56.   C.L. Wey, H. Wang, and C.-P. Wang, "A Self-timed Redundant-Binary to Binary Number Converter for Digital Arithmetic Processors," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Pro­cessors (ICCD ’95), Austin, TX, pp. 386-389, October 1995.

57.   T.-H. Pan.H.-S. Kay, Y. Chun, and C.L. Wey, "High-radix SRT Division with Speculation of Quotient Dig­its," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’95), Austin, TX, pp.479-482, October 1995.

58.   R. Huang and C.L. Wey, "A High-accuracy CMOS Oversampling Current Sample/Hold (S/H) Circuit Using Feedforward Approach," Proc. IEEE International Symposium on Circuits and Systems, Atlanta, GA, Vol. I, pp.65-68, May 1996.

59.   R. Huang and C.L. Wey, "A 5mW, 12-b, 50ns/b Switched-current Cyclic A/D Converter," Proc. IEEE Inter­national Symposium on Circuits and Systems, Atlanta, GA, Vol. I, pp.207-210, May 1996.

60.   C.-P. Wang, A.A. Hatzopoulos, and C.L. Wey, "A Test Paradigm for Analog and Mixed-signal Circuits and Systems," Proc. IEEE International Symposium on Circuits and Systems, Atlanta, GA, Vol. III, pp. 194-197, May 1996.

61.   C.-P. Wang and C.L. Wey, "Test Generation of Switched-current A/D Converters," Proc. 2nd IEEE Interna­tional Mixed Signal Testing Workshop, Quebec City, Canada, pp. 98-103, May 1996.

62. R. Huang, C.-P. Wang, C. Grunewald, and C.L. Wey, "Design of High-accuracy CMOS Oversampling Cur­rent Sample/Hold (S/H) circuits," Proc. of 39th Midwest Symp. on Circuits and Systems, Iowa, 939-942, Au­gust 1996.

63.   C.L. Wey and C.-P. Wang, "VLSI Implementation of a Fast Radix-4 SRT Division," Proc. of 39th Midwest Symp. on Circuits and Systems, Iowa, pp.65-68, August 1996.

64.   T.H. Pan and C.L. Wey, "An Efficient Gate Re-assignment Algorithm in Post Technology Mapping," Proc. of 39th Midwest Symp. on Circuits and Systems, Iowa, pp.363-366, August 1996.

65.   C.L. Wey, "On Design of Efficient Square Generator," IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’96), Austin, TX, pp. 506-513, October 1996.

66.   C.L. Wey, "Mixed-signal Testing -- a Review," (invited) IEEE International Conference on Electronics, Cir­cuits, and Systems, Rodos, Greece, pp.1064-1067, October 1996.

67.   C.-P. Wang and C.L. Wey, "Test Generation of Analog Switched-current Circuits," Proc. Asian Test Sympo­siums, Taiwan, pp.376-381, November 1996.

68.   C.-P. Wang and C.L. Wey, "Efficient Testability Design Methodologies for Mixed-signal/Analog Integrated Circuits," 3rd IEEE International Mixed Signal Testing Workshop, Seattle, WA, pp. 68-74, June 1997.

69.   W.-H. Huang and C.L. Wey, "Development of HDL-A Modeled Test Programs for Fault Diagnosis of Analog/Mixed-signal Circuits," 3rd IEEE International Mixed Signal Testing Workshop, Seattle, WA, pp. 3-14, June 1997.

70.   R. Huang, J.-S. Wang, and C.L. Wey, "A Fully Differential Switched-Current ADC with Improved Perfor­mance," (invited) Proc. 40th Midwest Symp. on Circuits and Systems, Davis, CA, pp.177-180, August 1997.

71.   C.L. Wey, "Development of Redesign Process for Digital VLSI Systems," Proc. 40th Midwest Symp. on Cir­cuits and Systems, Davis, CA, pp.1001-1004, August 1997.

72.   C.-P. Wang and C.L. Wey, "High-accurate CMOS Current Comparator," Proc. 40th Midwest Symp. on Cir­cuits and Systems, Davis, CA, pp.346-349, August 1997.

73.   W.-H. Huang and C.L. Wey, "Development of Automatic Test System for Mixed-signal/Analog Integrated Circuits," Proc. 40th Midwest Symp. on Circuits and Systems, Davis, CA, pp.1434-1437, August 1997.

74.   C.-P. Wang and C.L. Wey, "Development of Hierarchical Testability Design Methodologies for Mixed-sig­nal/Analog Integrated Circuits," Proc. International Conference on Computer Design (ICCD) , pp.468-473, Oc­tober 1997.

75.   M. Jimenez, M. Shanblatt, and C.L. Wey, "Mapping Multiplication Algorithms into a Family of LUT-based FPGAs," 1998 ACM/SIGDA Sixth International Symposium o Field Programmable Gate Arrays (FPGA'98), Monterey, CA, February 1998.

76.   M.A. Khalil and C.L. Wey, "Using Test Generation Techniques for Redesigning Digital VLSI Circuits with Incomplete Implementation Information," Proc. International Conference on Chip Technology, Hsinchu, Tai­wan, pp.146-152, April 1998.

77.   J.-S. Wang and C.L. Wey, "Accurate CMOS Switched-current Divider Circuits," Proc. IEEE International Symposium on Circuits and Systems, Monterey, CA, pp. 53-56 (Vol. I), May 1998.

78.   J.-S. Wang and C.L. Wey, "A 12-bit, 100ns/b, 1.9mW CMOS Switched-current Cyclic A/D Converter," Proc. IEEE International Symposium on Circuits and Systems, Monterey, CA, pp.416-419 (Vol. VI), May 1998.

79.   Y. Wan and C.L. Wey, "Efficient Algorithms for Binary Logarithmic Conversion and Addition," Proc. IEEE International Symposium on Circuits and Systems, Monterey, CA, pp.233-236 (Vol. V), May 1998.

80.   C.L. Wey and M.A. Khalil, "Redesignability Analysis of Digital VLSI Circuits with Incomplete Implementa­tion Information," Proc. IEEE International Symposium on Circuits and Systems, Monterey, CA, pp.147-150 (Vol. VI), May 1998.

81.   J.-S. Wang, W.-H. Huang, and C.L. Wey, "Built-In Testers for Analog/Mixed-Signal Circuits with CMOS Switched-Current Technique" Proc. of 4th IEEE International Mixed-Signal Workshop, Hague, Netherlands, May 1998.

82.   M.A. Khalil and C.L. Wey, "Redesign Strategies for Digital VLSI Circuits with Incomplete Implementation Information," IEEE Midwest Symposium on Circuits and Systems, Notre Dame, IN, pp.264-267, August 1998.

83.   J.-S. Wang and C.L. Wey, "A 10-b, 100MS/s, 2.8mW CMOS Switched-current DAC for Low-power/Low-voltage Signal Processing Applications," Proc. IEEE Midwest Symposium on Circuits and Systems, Notre Dame, IN, pp.526-529, August 1998.

84.   W.-H. Huang, J.A. Resh, and C.L. Wey, ""On Synthesis of Manufacturable and Testable Analog Integrated Circuits," Proc. IEEE Midwest Symposium on Circuits and Systems, Notre Dame,IN, pp.340-343, August 1998

85.   J.-S. Wang, R. Huang, and C.L. Wey, "Synthesis of Optimal Current Copiers for Low-power/Low-voltage Switched-current Circuits," Proc. IEEE Midwest Symposium on Circuits and Systems, Notre Dame, IN, pp.220-223, August 1998.

86.   J.-S. Wang, W.-H. Huang, and C.L. Wey, "Fault Simulation of Built-in Tester for CMOS Switched-current Circuits," Proc. IEEE Midwest Symp. on Circuits and Systems, Notre Dame, IN, pp. 212-215, August 1998..

87.   J.-S. Wang, and C.L. Wey, "Design of High-performance CMOS Switched-current D/A Converters for Low- power/Low-voltage Signal Processing Applications," Proc. IEEE International Conference on Electronics, Cir­cuits, and Systems, Lisboa, Portugal, pp.1.19-1.22, September 1998.

88.   C.L. Wey and W.-H. Huang, "Test Point Selection Process and Diagnosability Analysis for Analog Integrated Circuits," Proc. IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD ’98), Austin, TX, pp.582-587, October 1998.

89.   C.L. Wey, D.M. Aslam, and B. Kim, "Development of Embedded Testers Using Nano-Probes for Mnaufactur­ability Enhancement of Microelectronic Circuits and Systems", presented in DAPRA Tri-Service MEMS Based INSs Workshop, Alabama, December 1998.

90.   J.-S. Wang and C.L. Wey, "A 11-b, 100MS/s, 4.4mW CMOS Switched-current Digital-to-Analog Converter," Proc. IEEE Midwest Symposium on Circuits and Systems, Las Cruces, NM, pp.474-477, August 1999.

91.   J.-S. Wang and C.L. Wey, "Built-in Testers for Analog/Mixed-siganl Circuits with CMOS Switched-current Data Converters Techniques," Proc. IEEE E/IT Conference, Chicago, June 2000.

92.   M.A. Khalil and C.L. Wey, "REDCI3: Redesignability Check for Digital VLSI Circuits with Incomplete Im­plementation Information," Proc. IEEE Midwest Symp. on Circuits and Systems, E. Lansing, MI, pp.168-171, August 2000.

93.   D.T. Rover, B. Cheng, C.L. Wey, and M. Mutka, "Incorporating Large-scale Projects into a Multi-disci­plinary Approach to Embedded Systems," Proc. International Conference on Engineering Education, Taipei, Taiwan, pp.105-108, August 2000.

94.   J.-S. Wang and C.L. Wey, "A Low-voltage Low-power 13b Pipelined Switched-current Cyclic A/D Convert­er," Proc. the IEEE 2nd Dallas CAS Workshop on Low Power and Low Voltage Analog and Mixed Signal Cir­cuits & Systems, Dallas, Texas, March, 2001.

95.     M.A. Khalil and C.L. Wey, "High-voltage Stress Test Paradigms of Analog CMOS ICs for Gate-oxide Reli­ability Enhancement," Proc. IEEE VLSI Test Symposium, Marina del Rey, CA, 2001.

96.     M.A. Khalil and C.L. Wey, “Extreme-voltage Stress Vector Generation of Analog CMOS ICs for Gate-Oxide Reliability Enhancement,” Proc. International Test Conference (ITC), Baltimore, MD, 2001.

97.     C.L. Wey, “Design for Stressability of Analog CMOS ICs for Gate-oxide Reliability Enhancement.” IEEE International Mixed-Signal Workshop, June, 2003.

98.     C.L. Wey, “High-speed IC/SOC Design at National Central University,” (Invited) Proc. of US/Taiwan Summit Conference on Nano Technology and System-on-Chip Si-Soft Project, Los Angeles, CA, 2003.

99.     C.L. Wey, M.A. Khalil, J. Liu, and G. Wierzba, “Hierarchical Extreme-voltage Stress Test of Analog CMOS ICs for Gate-oxide Reliability Enhancement,” Proc. Great Lake Symp. On VLSI, Boston, MA, pp. 322-327, 2004.

100.         S. Quan and C.L. Wey, “A Noise Optimization Technique for Codesign of CMOS Radio-frequency Low Noise Amplifiers and Low-quality Spiral Inductors,” Proc. Great Lake Symp. On VLSI, Boston, MA, pp. 178-182, April, 2004.

101.         J.-F. Li, C.-C. Hsu., Huang, C.-D., and C.L. Wey, “Soft IP Generation for Reconfigurable Fast Adders,” Proc. Of 15th VLSI/CAD,Taiwan, August, 2004

102.         C.L. Wey, and M.Y. Liu, “Stress Test Pattern Generation for Analog CMOS ICs,” Proc. of 15th VLSI/CAD, Taiwan, August, 2004.

103.         J.-F. Li, Tseng, T.-W., Huang, J.-H, Yu, J.-D., and C.L. Wey, “Design of Reconfigurable Hybrid Carry-lookahead/Carry-select Adders,” Proc. of 15th VLSI/CAD, Taiwan, August, 2004.

104.         Wey, C,L, and M.Y. Liu, “Burn-in Stress Test of Analog ICs,” Proc. of Asian Test Symp., Taiwan, pp.360-365, November, 2004.

105.         J.-F. Li, Y.-C. Kuo, C.-D. Huang, T-W. Tseng, and C.L. Wey, “Design of Reconfigurable Carry Select Adders,” IEEE Asia-Pacific Conference on Circuits and Systems, Tainan, Taiwan, pp.825-828, December 2004

106.         C.L. Wey and J.-F. Li, “Design of Reconfigurable Array Multipliers and Multiplier-accumulators,” IEEE Asia-Pacific Conference on Circuits and Systems, Tainan, Taiwan, pp.37-40, December 2004.

107.         J.-F. Li, T.-W. Tseng, and C.L. Wey,”An Efficient Transparent Test Scheme for Embedded Memories”, Proc. Design, Automation and Test in Europe (DATE), Munich, Germany, pp.574-579, March 2005.

108.         S. Quan and C.L. Wey, “A Novel Reconfigurable Architecutre of Low-power Multiplier for Digital Signal Processing,” Proc. of IEEE International Symp. on Circuits and Systems, Kobe, Japan, May 2005.

109.         C.L. Wey, M.-Y. Liu, and S. Quan, “Stress Test of CMOS SRAMs for Reliability Enhancement,” Proc. of IEEE International Mixed-Signal Test Workshop (IMSTW), Cannes, France, June 2005.

110.         C.L. Wey, M.-Y. Liu, and S. Quan, “Reliability Enhancement of CMOS SRAMs,” Proc. of IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), Taipei, Taiwan, pp.146-151, August 2005.

111.         S. Quan and C.L. Wey, “Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress,” Proc. of the 16th VLSI Design/CAD Symposium, Hua-Lian, Taiwan, August 2005.

112.         S.-F. Lin, M.-T. Shiue, and C.L. Wey, “An Efficient Interpolation Strcuture for Symbol Timing Recovery ,” Proc. of the 16th VLSI Design/CAD Symposium, Hua-Lian, Taiwan, August 2005.

113.         A. Wey, Y.-B. Sun, and C.L. Wey, “Infrared-irradiated Fuel for Increased Fuel Conversion Efficiency,” AFS Society, International Topical Conferences & Exposition on Diesel and Gas Engine Emission Soultion, Ann Arbor, Michigan, September 2005.

114.         S. Quan and C.L. Wey, “Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress,” Proc. of IEEE Symp. on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, pp.563-572, October 2005.

115.         C.L. Wey, “Nanoelectronics: Silicon Technology Roadmap and Emerging Nanoelectronics Technology in Taiwan,” Proc. of the IEEE IECON’05, Raleigh, North Carolina, November, 2005.

116.         S. Quan, Q. Qiang, and C.L. Wey, “Design of a CMOS Operational Amplifier for Extreme-voltage Stress Test,” Proc. of IEEE 14th Asian Test Symposium, Kolkata, India, pp.70-73, December 2005.

117.         M.-T. Shiue and C.L. Wey, “Efficient Implementation of Interpolation Technique for Symbol Timing Recovery in DVB-T Transceiver Design,” Proceedings of 6th IEEE International Conference on Electro/Information Technology (EIT), E. Lansing, Michigan, pp.427-431, May 2006.

118.         C.L. Wey, “Residue-to-Binary Converters for High-speed Digital Signal Processing,” Proceedings of 6th IEEE International Conference on Electro/Information Technology (EIT), E. Lansing, Michigan, pp.421-426,  May 2006.

119.         T.-H. Tsai, Y.-T. Wang, J.-H. Hung, and C.L. Wey, “Compressed Domain Content-based Retrieval of MP3 Audio Example Using Quantization Tree Indexing and Melody-line Tracking Method,” Proc. of IEEE International Symp. on Circuits and Systems, Greece, pp.5491-5494, May 2006.

120.         C.-S. Huang and C.L. Wey, “Reliability Enhancement of CMOS PLLs,” Proc. of the 17th VLSI Design/CAD Symposium, Hua-Lian, Taiwan, August 2006.

121.         C.L. Wey, “Efficient Rectlinear Steiner Tree Construction with Rectangular Obstacels,” Proc. of the WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing (CSECS ’06), Dallas,, Texas, November 2006.

122.         C.L. Wey and C.-S. Huang, “Design of Reliable CMOS Phase Locked Loops,” Proc. of the 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France, December 2006.

123.         C.L. Wey, S.-Y. Lin, T.-H. Tsai, and M.T. Shiue, “Efficient Implementation of Interpolation Technique for Symbol Timing Recovery,” Proc. of the WSEAS International Conference on Circuits, Systems, Signal and Telecommunication (CISST ’07), Gold Coast, Queensland, Austrial, January 2007.

124.         C.L. Wey, W.-C. Tang, and S-Y. Lin, “Efficient Memory-based FFT Architectures for Digital Video Broadcasting (DVB-T/H)” VLSI-DAT, Hsinchu, Taiwan, April,2007.

125.       C.L. Wey and S.-Y. Lin, “A Pipelined Divider with a Small Lookup Table,” Proc. of 7thWSEAS International Conference on Instrumentation, Measurement, Circuits and Systems (IMCS ’07), Hangzhou, China, April, 2007.

126.       C.L. Wey, W.-C. Tang, and S-Y. Lin, “Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications,” Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Porto Alegre, Brazil, May 2007.

127.       C.L. Wey, S.-Y. Lin, and W.-C. Tang, “Efficient Memory-Based FFT Processors for OFDM Applications” Proc. of the 7th IEEE International Conference on Electro/Information Technology (EIT), Chicago, ILL, May 2007. (Outstanding Paper)

128.       C.L. Wey and S.-Y. Lin, “VLSI Implementation of Residue-to-Binary Converters for Digital Signal Processing” Proc. of the 7th IEEE International Conference on Electro/Information Technology (EIT), Chicago, ILL, May 2007.

129.       S.-Y. Lin, W.-C. Tang, M.-T. Shiue, and C.L. Wey, “High-speed, low-cost Parallel Memory-based FFT Processor for OFDM Applications,” Proc. of the 18th VLSI Design/CAD Symposium, Hua-Lian, Taiwan, August 2007.

130.       C.-K. Liau, S.-Y. Lin, T.-H. Tsai, and C.L. Wey, “A Partially Parallel Low-density Parity Check Code Decoder with Reduced Memory for Long Code-length,” Proc. of the 18th VLSI Design/CAD Symposium, Hua-Lian, Taiwan, August 2007.

131.       Y.-X. Yang, J.-F. Li, H.-N. Liu, and C.L. Wey, “Design of Cost-Efficient Memory-Based FFT Processors Using Single-port Memories,” Proc. Of IEEE International SOC Conference, Hsinchu, Taiwan, Septermber 2007.

132.       C.L. Wey and S.-Y. Lin , “High-speed, Low Cost Parallel Memory-based FFT Processors for OFDM Applications,” Proc. IEEE International Conference on Electronics, Circuits, and Systems, Marrakech, Morocco, December 2007.

133.       C.-M. Huang, C.-M. Wu., C.-C. Yang, and C.L. Wey, “PrSoC: Programmable System-on-Chip (SoC) for Silicon Prototyping,” Proc. IEEE International Symp. on Circuits and Systems, Seatle, WA, May 2008.

134.       P.-W. Luo, J.-E. Chen, C.L. Wey, C.-H. Su, H.-C. Liang, Y.-F. Huang, and W.-C. Wu, “On the Dedelopment of Spatial Correlation Analysis for Yield Ehancement of Mixed-signal Integrated Circuits,” Proc. European Test Symp., Italy, May 2008.

135.       C.-M. Huang, C.-M. Wu, C.-C. Yang, K.-J. Lee, and C.L. Wey, ”Programmable System-on-Chip (SoC) for Silcion Prototyping,” Proc. International Symp. on Industrial Electronics, Cambridge, UK, June 2008.

136.       S.-Y. Lin and C.L. Wey, “A Low-Cost Continuous-flow FFT Processor for UWB Applications,” Proc. of the 19th VLSI Design/CAD Symposium, Pingdong, Taiwan, August 2008.

137.       C.-W. Lin, C.-H. Su, and C.L. Wey, “A Cascaded Sigma-Delta Modulator with DAC Error Cancellation Scheme,” Proc. of the 19th VLSI Design/CAD Symposium, Pingdong, Taiwan, August 2008.

138.       C.L. Wey, S.-Y. Lin, H.-S. Wang, and C.-M. Huang, “A Low-Cost Continuous-Flow FFT Processor for Ultra-Wideband Applications,” Proc. of the International Conference on Advances in Electronics and Micro-electronics (ENICS 2008), Valencia, Spain, Septemner 2008.

139.       W.-C. Tsai, M.-D. Shieh, W.-C. Lin, and C.L. Wey, “Design of Square Generator with Small Look-up Table," Proc. of IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, Nov. 2008.

140.       C.L. Wey and S.-Y. Lin, “A Low-Cost Continuous Flow Parallel Memory-based FFT Processor for Ultra-wideband (UWB) Applications," Proc. of IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, Nov. 2008.

141.       T.-H. Chien, C.-S., Lin, Y.-Z. Juang, C.-M. Huang, and C.L. Wey, “An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-locked Loops, “ IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2009.

142.       P.-W. Luo, J.-E. Chen, and C.L. Wey, “Yield Evaluation of Analog Placement with Arbitrary Capacitor Ratio,” Proc. International Symp. on Quality Electronic Design (ISQED 2009), San Jose, CA, March 2009.

143.       C.-M. Huang, C.-M. Wu, C.-C. Yang, S.-L. Chen, and C.L. Wey, “Implementation and Prototyping of a Complex Multi-project System-on-a-Chip,” Proc. International Symp. on Circuits and Systems, Taipei, Taiwan, May 2009.

144.       J.-J. Wu and C.L. Wey, “A Partially Parallel Low-density Parity Check Code Decoder,” Proc. Electronic Technology Symposium, Kaohsiung, Taiwan, June 2009.

145.       C.-C. Yang, C.-M.Huang, C.-M. Wu, W.-D. Chien, S.-L. Chen, C.-S. Chen, J.-J. Wang, and C.L. Wey, “A Fully Configurable and Modulized Platform for Multi-project SoC Design,” Proc. Electronic Technology Symposium, Kaohsiung, Taiwan, June 2009.

146.       K.-L. Leu﹐Y.-Y. Chen, C.-L. Wey, and J.-E. Chen, “Robustness Investigation of the FlexRay System,” Proc. IEEE Symposium on Industrial Embedded Systems, Lausanne, Switzerland, July 2009.

147.       H.-W. Huang, C.L. Wey, and J.E. Chen, “Tango-RM: An Enhanced Switches Scheme of Resistor-string Successive Reference Generator,” Proc. VLSI Test Technology Workshop (VTTW), Nantou, Taiwan, July 2009.

148.       C.-M. Huang, Y.-T. Chang, J.-Y. Hsieh, C.-M. Wu, C.-Y. Lin, H.-T. Wu, W.-D. Chien, J.-J. Wang, and C.L. Wey, “MORFPGA: A Modularized FPGA Development Platform for IC Design Education and Contests,” Proc. International Conference on Engineering Education & Research (iCEER), pp.66-72, Seoul, Korea, August, 2009.

149.       T.-H. Chien, C.-S. Lin, C.L. Wey, Y.-Z. Juang, and C.-M. Huang, “High-speed and Low-power Programmable Frequency Divider,” Proc. International Symp. On Circuits and Systems, Paris, France, May 2010.

150.       C.-S. Lin, T.-H. Chien, and C.L. Wey, “An Effective Phase Detector for Phase-locked Loops with Wide Cature Range and Fast Acquistion Time,” Proc. International Symp. On Circuits and Systems, Paris, France, May 2010.

151.       K.-L. Leu, Y.-Y. Chen, C.L. Wey, J.-E. Chen, and C.-H. Huang, “A Bayesian Network Reliability Modeling for FlexRay Systems,” Proc. International Conference on Information and Communication Technologies (ICICT 2010), Tokyo, Japan, May 2010.

152.       K.-L. Leu, Y.-Y. Chen, C.L. Wey, and J.-E. Chen, “A Verfication Flow for FlexRay Communication robustness Compliant with IEC 61508,” Proc. IEEE 2nd International Conference on Industria; Mechatronics and Automation (ICIMA 2010), Wuhan, China, May 2010.

153.       F.-C. Liu, Y.-J. Hsieh, Y.-J., C.-C. Wang, and C.L. Wey, “A Nonlinear Lithium Battery Model for Charging and Discharging,” Proc. of 2010 Electronic Technology Symposium, Kaohsiung, Taiwan, June 2010.

154.       K.-L. Leu, Y.-Y. Chen, C.L. Wey, and J.-E. Chen, “RobustnessAnalysis of the FlexRay System through Fault Tree Analysis,” Proc. IEEE International Conference on Vehicular Electronics and Safety (ICVES 2010), Shandong, China, July 2010.

155.       T.-H. Chien, C.-S. Lin, and C.L. Wey, “A Forward Phase Detector for GSampls/s Phase-locked Loops,” Proc. of the International Conference on Advances in Electronics and Micro-electronics (ENICS 2010), Venice, Italy, July 2010.

156.       K.-C. Yang, Y.-T., Chang, C.-M. Wu, C.-M. Huang, C.-T. Kuo, and C.L. Wey, “Case Study: An Universal Study Platform for ESW Education,” Proc. of the International Conference on Engineering Education & Research (iCEER), Gliwice, Poland, pp.1-8, July 2010.

157.       C.M. Huang, C.-M. Wu, Y.-T. Chang, C.-Y. Chen, Y.-S. Lin, C.-T. Kuo, T.-C. Liu, and C.L. Wey, “MorFPGA: A Modularized FPGA-based Embedded System Development Platform,“ Proc. of VLSI/CAD Symposium, Kaohsiung, Taiwan, August 2010.

158.       Y.-T. Chang, C.M. Huang, C.-M. Wu, C.-Y. Chen, Y.-S. Lin, C.-T. Kuo, C.L. Wey, and T.-C. Liu, “MorFPGA: A Modularized FPGA-based Embedded System Development Platform,“ Proc. of the 16th workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI 2010), Taipei, Taiwan, Oct. 2010.

159.       C.-C. Yang, C.-Y. Lin, H.-M. Lin, Y.-C. Shih, H.-T. Wu, S.-L. Chen, T.-C. Wang, C.-M. Wu, C.M. Huang, and C.L. Wey, “Concord: A Configurable SoC Prototyping Platform,” Proc. of the 16th workshop on Synthesis and System Integration of Mixed Information Technology (SASIMI 2010), Taipei, Taiwan, pp. 31-36, Oct. 2010.

160.       C.M. Huang, C.-M. Wu, Y.-T. Chang, C.-Y. Chen, Y.-S. Lin, C.-T. Kuo, T.-C. Liu, and C.L. Wey, “A Modularized FPGA-Based Embedded System Development Platform,“ Proc. of the 36th Annual Conference of the IEEE Industrial Electronics Society (IECON-2010), Phoenix, Arizona, November 2010.

161.       C.L. Wey, “A Modularized FPGA Development Platform,” Proc. of the 12th Cross-Strait Information Technology Conference (CSIT2010), Nanjing, China, pp. 161-164, November 2010.

162.       C.L. Wey, “Design for Stressability of Analog CMOS Circuits for Gate-Oxide Reliability Enhancement,” 60th IFIP WG Workshop, Taoyuan, Taiwan, July 2011. (Invited Paper)

163.       C.-C. Huang, J.-E. Chen, P.-W. Luo, and C.L. Wey, “A Fast Interconnection Capacitance Estimation in Capacitor Array Block,” . VLSI Test Technology Workshop (VTTW), Nantou, Taiwan, July 2011.

164.       C.L. Wey, K.-C Chang, C.-H. Hsu, F.-C. Liu, and S.-W. Chen, “Lithium Battery Models for Battery Charging and System Loading,” Proc. of IEEE International Midwest Symp. on Circuits and Systems, Seoul, Korea, August 2011.

165.       C.-Hsu, K.-C. Chang, C. Ouyang, K.-Y. Liao, and C.L. Wey, “On the Implementation of CAN Buses to Battery Management Systems” Proc. of IEEE International Midwest Symp. on Circuits and Systems, Seoul, Korea, August 2011.

166.       C.-C. Huang, J.-E. Chen, P.-W. Luo, and C.L. Wey, “Yield-aware Placement Optimization for Switched-capacitor Analog Integrated Circuits,” Proc. of 24th IEEE International SoC Conference (SOCC 2011), Taipei, Taiwan, September 2011.

167.       C.L. Wey, K.-C. Chang, C.-I. Chiu, C.-H. Hsu, and G.-N. Sung, “Design of Ultra-Wide-Load, High-Efficiency DC-DC Buck Converters,” Proc. of IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec. 2011, Beirut, Lebanon, December 2011.

168.       P.-C. Jui and C.L. Wey, “Collaboration between Academia and Technology Research Institutes in Taiwan,” Proc. of European Workshop on Microelectronics Education (EWME), Grenoble, France, May 2012.

169.       P.-C. Jui, G.-N. Sung, and C.L. Wey, “Efficient Algorithm and Hardware Implementation of 3N for Arithmetic and for Radix-8 Encodings,” Proc. of IEEE Midwest Symp. on Circuits and Systems, Boise, Idaho, Auguster, 2012.

170.       S.-K. Chang and C.L. Wey, “A Fast 64-bit Hybrid Adder Design in 90nm CMOS Process,” Proc. of IEEE Midwest Symp. on Circuits and Systems, Boise, Idaho, Auguster, 2012.

171.       CL. Wey, Z.-Y. Li, K.-C. Chang, G.-N. Sung, and D.K. Wey, “A Fast Hysteretic Buck Converter with Adaptive Ripple Controller,” Proc. of IEEE Midwest Symp. on Circuits and Systems, Boise, Idaho, Auguster, 2012.

172.       P.-W. Luo, T. Wang, C.L. Wey, L.-C. Cheng, B.-L. Sheuu, and Y. Shi, “Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits,” Proc. of IEEE Computer Scieity Annual Symp. on VLSI (ISVLSI), August, 2012. (Invited Paper).

 

Tutorial/Short Course Lecturer

·         “Mixed-Signal IC Design,” Semina Series (6 hours), Workshop on Mixed-signal IC Design, National Science Council/National Tamkang University,  July 2001.

·         “Mixed-Signal IC Testing”, Niational Science Council, National Central University, Taiwan, Feb. 2000.

·         "Design and Test of Analog/Mixed-Signal Integrated Circuits," International Conference on Chip Tech­nology, Hsinchu, Taiwan, April 1998..

·         "Design, Testing, and Fault Diagnosis of Analog/Mixed-Signal Integrated Circuits," Mixed-Signal Prod­ucts, Semiconductor Group, Texas Instrument Inc., Dallas, Texas, July 1997.

·         "Mixed-Signal Fault Models and Design-for-Test", IEEE Asian Test Symp., Hsinchu, Taiwan, No­v. 1996.

·         "Mixed-Signal Testing -- a Review," IEEE International Conference on Electronics, Circuits, and Systems, Rodos, Greece, October 1996.

·         "Technology for Integrated Circuit (IC) Design and Fabrication", Institute of International Education, E. Lansing, Michigan, February 1995. Short-term US-based training for USAID Regional Support Mission for East Asia (RSM/EA) and the National Science and Technology Department Agency (NSTDA) conducted by IIE through the Department of Technical and Economic Corporation (DTEC) in connection with the Science and Technology for Development Project (Project No. 493-0340)

·         "Some Issues on Technology Mapping for Standard Cells in Logic Synthesis,"4th VLSI/CAD Workshop, Nantou, Taiwan. August 1993.

·         "Design and Test of Current-Mode Signal Processing Circuits for Sensor Array Implementation," Na­tional Chiao-Tung University, November 1992.

·         "Analog IC Design and Synthesis," 1992 Workshop on VLSI Designs, Taipei, Taiwan, July 1992.

·         "Synthesis and Design of Asynchronous Sequential Circuits and Systems,"  Taipei, Taiwan, July 1992

·         "Built-In Self-Test Design of Analog and Digital Circuits," 1990 Work­shop on VLSI Testing, National Chiao-Tung University, Taiwan, August 1990.

·         "Tutorial on Synthesis for Testability,"Workshop on Synthesis and Testability, National Taiwan University, Taiwan., May 1990.

·         "Tutorial on Logic Synthesis," Workshop on Synthesis and Testability, National Taiwan University, Taiwan, May 1990.

·         "Tutorial on Synthesis for Testability", 2nd Workshop on CAD for VLSI, Taiwan, March 1990. 

·         "Fault-tolerant VLSI Array Structures," Workshop on Fault-tolerant Computing, Microelectronics and Information Center, National Chiao-Tung Univ., June 1989

 

Pattents

1.         “Carrier Structure of SoC with Custom Interface,” US Patent, 7,755,177 B2 (7/13/2010). (Granted), Taiwan Patent, 355055 (12/21/2011-10/8/2028).

2.          “Edge-missing Detector Structure,” US Patent No. 7,859,313 B2 (12/28/2010). (Granted)

3.          “Programmable Frequency Divider with Full Dividing Range,” US Patent No. 12/495,107 (Filed: 6/30/2009) (Pending)

4.          “Fabrication method for System-on-chip (SoC) modules,” US Patent No. 12/570,049, (Filed: 9/30/2009) (Pending)

5.          “Multi Layer System Chip Module Architectures,” US Patent No. 12/685,723, (Filed: 1/12/2010) (Pending)

6.          “Method for Manufacturing 3-axial Sensing MEMS Device on Compatible CMOS Platform,” US Patent No. 12/652,068, (Filed: 1/5/2010) (Pending)

7.          “Hydrogen Ion Sensitive Field Effect Transistor and Manufacturing Method Therefore,” US Patent No. 12/724,435, (Filed: 3/16/2010) (Pending)

8.          “Unitized Charging and Discharging Battery Management System and Programmable Battery Management Module Therefore,” US Patent No. 12/728,288, (Filed: 3/22/2010) (Pending)

9.          “Three-Dimensional SoC Structure Stacking By Multiple Chip Modules,” US Patent No. 12/752,345, (Filed: 4/1/2010) (Pending)

10.      “Virtual Optical Storage Device,” US Patent, No. 12/728,288, (Filed: 3/22/2010) (Pending)

11.      “Virtualized Peripheral Hardware Platform System,” US Patent, No. 12/961,783, (Filed: 12/7/2010) (Pending)

12.  “Yield Evaluator of Mixed-Signal Circuit Using Spatial Correlation Analysis,” US Patent, No. 20100088655, (Filed: 4/2010).