Publications (Google Scholar Citations)

• JOURNAL PAPERS

  1. J.-F. Li, S.-K. Lu, S.-A. Hwang, and C.-W. Wu, ``Easily testable and fault tolerant FFT butterfly networks," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing , vol.47, no.9, pp. 919-929, Sep. 2000.
  2. C.-W. Wu, J.-F. Li, and C.-T. Huang, ``Core-based system-on-chip testing: challenges and opportunities," J. Chinese Institute of Electrical Engineering (Special Issue on Design and Test of System-on-Chip), vol. 8, no. 4, pp.335-353, Nov. 2001.
  3. J.-F. Li and C.-W. Wu,``Efficient FFT network testing and diagnosis schemes," IEEE Trans. Very Large Scale Integration systems, vol. 10, no. 3, pp. 267-278, June 2002.
  4. J.-F. Li, R.-S. Tzeng and C.-W. Wu, ``Diagnostic data compression for embedded memories with built-in self-test,'' J. Electronic Testing: Theory and Application (Special Issue on Plug-and-Play Test Automation for System-on-a-Chip), vol.18, no.4, pp. 515-527, Aug. 2002.
  5. J.-F. Li, H.-J. Huang, J.-B. Chen, C.-P. Su, C.-W. Wu, C. Cheng, S.-I. Chen, C.-Y. Hwang and H. P. Lin, ``A hierarchical test methodology for system-on-chip'', IEEE Micro (Special Issue on Design and Test of Systems on Chip), vol.22 no.5, pp. 69-81, Sep/Oct., 2002.
  6. C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu and H.-P. Lin, ``A built-in self-test scheme with diagnostic support for embedded SRAM,'' J. Electronic Testing: Theory and Application , vol.18 no.6, pp. 637-647, Dec. 2002.
  7. J.-F. Li, R.-S. Tzeng and C.-W. Wu,``Testing and diagnosis methodologies for embedded content addressable memories,'' J. Electronic Testing: Theory and Application, vol.19, no.2, pp. 207-215, Apr. 2003.
  8. C.-T. Huang, C.-F. Wu, J.-F. Li and C.-W. Wu,``Built-in redundancy analysis for memory yield improvement,'' IEEE Trans. Reliability, vol. 52, no. 4, pp. 386-399, Dec. 2003.
  9. J.-F. Li,``Diagnosing binary content addressable memories with comparison and RAM faults,'' IEICE Trans. Information and Systems, vol.E87-D, no. 3, pp. 601-608, March 2004.
  10. J.-F. Li,``Efficient block-level connectivity verification algorithms for embedded memories,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol.E87-A no.12 pp.3185-3193, Dec. 2004.
  11. J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu,``A built-in self-repair design for RAMs with 2-D redundancies,'' IEEE Trans. Very Large Scale Integration Systems, vol.13, no.6, pp. 742-745, June 2005.
  12. J.-F. Li,``Testing ternary content addressable memories with comparison faults using march-like tests,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.26, no.5, pp. 919-931, May 2007.
  13. Y.-J. Huang and J.-F. Li,``Testing ternary content addressable memories with active neighborhood pattern sensitive faults ,'' IET Proc. Computers and Digital Techniques (formerly IEE Proc. Computers and Digital Techniques), vol.1, no.3, pp. 246-255, May 2007.
  14. R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu,``RAISIN: a tool for evaluating redundancy analysis schemes in repairable embedded memories,'' IEEE Design and Test of Computers, vol.24, no.4, pp. 386-396, July-August 2007.
  15. J.-F. Li,``Transparent test methodologies for random access memories with/without ECC,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.26, no.10, pp. 1888-1893, Oct. 2007.
  16. C.-D. Huang, J.-F. Li, and T.-W. Tseng,``ProTaR: an infrastructure IP for repairing RAMs in SOCs,'' IEEE Trans. Very Large Scale Integration Systems, (Special section on system-on-chip integration: challenges and implications) vol.15, no.10, pp. 1135-1143, Oct. 2007.
  17. J.-F. Li and C.-D. Huang,``An efficient diagnosis scheme for RAMs with simple functional faults,''IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol.E90-A, no.12 pp. 2703-2711, Dec. 2007.
  18. D.-M. Chang, J.-F. Li, and Y.-J. Huang,``A built-in redundancy-analysis scheme for random access memories with two-level redundancy,'' J. Electronic Testing: Theory and Application, vol.24, no.1, pp. 181-192, Jan. 2008.
  19. H.-M. Shieh and J.-F. Li,``A multi-code compression scheme for test time reduction of system-on-chip designs," IEICE Trans. Information and Systems, vol. E91-D, no. 10, pp.  2428-2434, Oct. 2008.
  20. H.-N. Liu, Y.-J. Huang, and J.-F. Li, ``Memory built-in self test in multi-core chips with mesh-based networks," IEEE Micro, vol.29, no.5, pp. 46-55, Oct./Sept., 2009.
  21. J.-F. Li, ``Testing comparison and delay faults of TCAMs with asymmetric cells," IEEE Trans. Very Large Scale Integration Systems, vol.18, no.6, pp. 912-920, June 2010.
  22. T.-W. Tseng, J.-F. Li, and C.-C. Hsu, ``ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs," IEEE Trans. Very Large Scale Integration Systems, vol.18, no.6, pp. 921-932, June 2010.
  23. J.-F. Li, T.-W. Tseng, and C.-S. Hou, ``Reliability-enhancement and self-repair schemes for RAMs with static and dynamic faults," IEEE Trans. Very Large Scale Integration Systems, vol.18, no.9, pp. 1361-1366, Sept. 2010.
  24. T.-W. Tseng, Y.-J. Huang, and J.-F. Li,"DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SOCs," IEEE Trans. on Computer-Aided Design in Integrated Circuits and Systems, vol. 29, no. 10, pp. 1628-1639, Oct. 2010.
  25. J.-F. Li, Y.-J. Huang, and Y.-J. Hu,"Testing random defect and process variation induced comparison faults of TCAMs with asymmetric cells," IEEE Trans. on Computer-Aided Design in Integrated Circuits and Systems, vol. 29, no. 11, pp. 1843-1847, Nov. 2010.
  26. T.-W. Tseng, J.-F. Li, and C.-S. Hou, ``A built-in method to repair SoC RAMs in parallel," IEEE Design and Test of Computers, vol. 27, no. 6, pp. 46-57, Nov./Dec. 2010.
  27. T.-W. Tseng and J.-F. Li, ``SEBIST: an soft-error tolerant built-in self-test scheme for random access memories," Journal of Information Science and Engineering (JISE), vol., no., pp. -, vol. 27, no. 2, pp. 643-656, March 2011.
  28. T.-W. Tseng and J.-F. Li, ``A low-cost built-in redundancy-analysis scheme for word-oriented RAMs with 2D redundancy," IEEE Trans. Very Large Scale Integration Systems, vol. 9, no. 11, pp. 1983-1995, Nov. 2011.
  29. C.-S. Hou, J.-F. Li, and T.-W. Tseng, "Memory built-in self-repair planning framework for RAMs in SOCs," IEEE Trans. on Computer-Aided Design in Integrated Circuits and Systems, vol. 30, no. 11, pp. 1731-1743, Nov. 2011.
  30. T.-J. Chen, J.-F. Li, and T.-W. Tseng, "Cost-efficient built-in redundancy analysis with optimal repair rate for RAMs," IEEE Trans. on Computer-Aided Design in Integrated Circuits and Systems, vol. 31, no. 6, pp. 930-940, June 2012.
  31. H.-S. Yang, Y.-J. Huang, and J.-F. Li,"A low-power ternary content addressable memory with Pai- Sigma matchlines," IEEE Trans. on Very Large Scale Integrated Circuits and Systems, vol. 20, no. 10, pp. 1909-1913, Oct. 2012.
  32. Y.-J. Huang and J.-F. Li, "Built-in self-repair scheme for the TSVs in 3D ICs," IEEE Trans. on Computer-Aided Design in Integrated Circuits and Systems, vol. 31, no. 10, pp. 1600-1613, Oct. 2012.
  33. Y.-J. Huang and J.-F. Li,"Low-cost self-test techniques for small RAMs in SOCs using enhanced IEEE 1500 test wrappers," IEEE Trans. on Very Large Scale Integrated Circuits and Systems , vol. 20, no. 10, pp. 2123-2127, Nov. 2012.
  34. J.-F. Li,"Testing and diagnosing comparison faults of TCAMs with asymmetric cells," IEEE Trans. on Computers , vol. 61, no.11, pp.  1576-1587 , Nov. 2012.
  35. C.-K. Lai, Y.-J. Huang, and J.-F. Li,"A self-repair technique for content addressable memories with address-input-free writing function," Journal of Information Science and Engineering (JISE), vol. 29, no. 3, pp.  493-507 , March 2013.
  36. C.-W. Chou, Y.-J. Huang, and J.-F. Li, "A built-in self-repair scheme for 3D RAMs with inter-die redundancy," IEEE Trans. on Computer-Aided Design in Integrated Circuits and Systems, vol. 32, no. 4, pp. 572-583, April 2013.
  37. Y.-J. Huang and J.-F. Li, "Yield-enhancement schemes for multi-core processor and memory stacked 3D ICs," ACM Trans. on Embedded Computing Systems, Vol.13 , Issue 3s. No. 106, pp. 1-22, March 2014.
  38. C.-S. Hou, J.-F. Li, and T.-J. Fu,"A BIST scheme with the ability of diagnostic data compression for RAMs," IEEE Trans. on Computer-Aided Design in Integrated Circuits and Systems, vol. 33, no. 12, pp. 2020-2024, Dec. 2014.
  39. C.-S. Hou and J.-F. Li,``Testing disturbance faults in various NAND flash memories,'' J. Electronic Testing: Theory and Application, vol. 30, no. 6, pp. 643-652, Dec. 2014.
  40. C.-W. Chou, J.-F. Li, Y.-C. Yu, C.-Y. Lo, D.-M. Kwai, and Y.-F. Chou,"Hierarchical test integration methodology for 3D ICs," IEEE Design and Test , vol. 32, no.4 , pp.  59-70, July-August 2015.
  41. C.-S. Hou and J.-F. Li,"High repair-efficiency BISR scheme for RAMs by reusing bitmap for bit redundancy," IEEE Trans. on Very Large Scale Integrated Circuits and Systems , vol. 23, no. 9, pp. 1720-1728, Sept. 2015.
  42. J.-F. Li and J.-L. Huang,"Report on 2017 IEEE Asian Test Symposium," IEEE Design and Test , vol. 35, no. 2, pp.  103-104, April 2018.
  43. V. P.-H. Hu, C.-W. Su, Y.-W. Lee, Y.-Y. Ho, C.-C. Cheng, T.-C. Chen, T. Y.-T. Hung, J.-F. Li, Y.-G. Chen, and L.-J. Li,"Energy-efficient monolithic 3D SRAM cell with BEOL MoS2 FETs for SoC scaling," IEEE Trans. on Electronic Devices, vol. , no. , pp.  -, Aug. 2020.
  44. T.-L. Tsai, J.-F. Li, C.-L. Hsu, and C.-T. Sun, "Testing of in-memory-computing memories with 8T SRAMs," Microelectronics Reliability, vol. no., pp. -, June 2021.
  45. W.-C. Cheng, S.-H. Huang, and J.-F. Li,``Hardware trojan design with low overhead and high destructiveness for STT-MRAM-based CIMs,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol., no., pp. -, Feb. 2025 (accepted).

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• CONFERENCE PAPERS

  1. J.-F. Li, S.-A. Hwang, S.-K. Lu, and C.-W. Wu, ``Fault tolerant FFT butterfly network design,'' in Proc. 9th VLSI Design/CAD Symp., (Nantou), pp. 403-406, Aug. 1998.
  2. J.-F. Li and C.-W. Wu, ``Design for C-diagnosable FFT networks,'' in Proc. 10th VLSI Design/CAD Symp., (Nantou), pp. 191-194, Aug. 1999.
  3. J.-F. Li and C.-W. Wu, ``Testable and fault tolerant design for FFT networks ,'' in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT) , (Albuquerque), pp. 201-209, Nov. 1999.
  4. C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu and H.-P. Lin, ``A built-in self-test and self-diagnosis scheme for embedded SRAM,'' in Proc. IEEE Asian Test Symp. (ATS), (Taipei), pp. 45-50, Dec. 2000.
  5. J.-F. Li and C.-W. Wu, ``Memory fault diagnosis by syndrome compression,'' in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE), (Munich), pp. 97-101, Mar. 2001.
  6. J.-F. Li, R.-S. Tzeng and C.-W. Wu, ``Using syndrome compression for memory built-in self-diagnosis,'' in Proc. IEEE Int. Symp. VLSI Technology, Systems, and Applications (VLSI-TSA), (Hsinchu), pp. 303-306, Apr. 2001.
  7. J.-F. Li, K.-L. Cheng, C.-T. Huang and C.-W. Wu, ``March-based diagnosis algorithms for stuck-at and coupling faults in RAMs,'' in Proc. IEEE Int. Test Conf. (ITC), (Baltimore), pp. 758-767, Oct. 2001.
  8. H.-J. Huang, J.-F. Li, C.-P. Su, C.-W. Wu, C. Cheng, S.-I. Chen, C.-Y. Hwang and H. P. Lin,``Test wrapper design automation for system-on-chip'', in Proc. 12th VLSI Design/CAD Symp., (Hsinchu), Aug. 2001.
  9. J.-B. Chen, J.-F. Li, C.-P. Su, C.-W. Wu, C. Cheng, S.-I. Chen, C.-Y. Hwang and H. P. Lin, ``A test controller for system-on-chip designs with test wrappers'', in Proc. 12th VLSI Design/CAD Symp., (Hsinchu), Aug. 2001.
  10. J.-F. Li, H.-J. Huang, J.-B. Chen, C.-P. Su, C.-W. Wu, C. Cheng, S.-I. Chen, C.-Y. Hwang and H. P. Lin, ''A hierarchical test scheme for system-on-chip designs'', in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE), (Paris), pp. 486-490, Mar. 2002.
  11. J.-F. Li, R.-S. Tzeng and C.-W. Wu,``Testing and diagnosing embedded content addressable memories,'' in Proc. IEEE VLSI Test Symp. (VTS), (Monterey, California), pp. 389-394, Apr. 2002.
  12. R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu,``A simulator for evaluating redundancy analysis algorithms of repairable embedded memories,'' in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), (Isle of Bendor, France), pp. 68-73, July. 2002.
  13. R.-F. Huang, L.-M. Denq, C.-W. Wu, and J.-F. Li,``A testability-driven optimizer and wrapper generator for embedded memories,'' in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), (San Jose), pp. 53-56, July, 2003.
  14. J.-F. Li,``A diagnosis scheme for binary content addressable memories,'' in Proc. 14th VLSI Design/CAD Symp., (Hualien), pp. 457-460, Aug. 2003.
  15. J.-F. Li,``Verification algorithms for memories with signal misplaced faults,'' in Proc. 14th VLSI Design/CAD Symp., (Hualien), pp. 325-328, Aug. 2003.
  16. J.-F. Li, J.-C. Yeh, R.-F. Huang, C.-W. Wu, P.-Y. Tsai, A. Hsu, and E. Chow,``A built-in self-repair scheme for semiconductor memories with 2-D redundancies,'' in Proc. IEEE Int. Test Conf. (ITC), (Charlotte), pp. 393-402, Sept. 2003.
  17. J.-F. Li, C.-C. Hsu, C.-D. Huang, and C.-L. Wey,"Soft IP generator for reconfigurable fast adders," in Proc. 15th VLSI/CAD Symp., (Pintung), Aug. 2004.
  18. J.-F. Li, T.-W. Tseng, Y.-J. Huang, J.-D. Yu, and C.-L.Wey, "Design of reconfigurable hybrid carry-lookahead/carry-select adders," in Proc. 15th VLSI/CAD Symp., (Pintung), Aug. 2004.
  19. J.-F. Li and Y.-C. Kuo, "Testing ternary content addressable memories," in Proc. 15th VLSI/CAD Symp., (Pintung), Aug. 2004.
  20. J.-F. Li and C.-D. Huang, "An efficient diagnosis scheme for random access memories," in Proc. IEEE Asian Test Symp. (ATS), (Pintung), pp. 277-282, Nov. 2004.
  21. J.-F. Li and C.-C. Hsu, "Efficient test methodologies for conditional sum adders," in Proc. IEEE Asian Test Symp. (ATS), (Pintung), pp. 319-324, Nov. 2004.
  22. J.-F. Li, Y.-C. Kuo, C.-D. Huang, T.-W. Tseng, and C.-L. Wey, "Design of reconfigurable carry select adders," in Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS), (Tainan), pp. 825-828, Dec. 2004.
  23. C.-L. Wey and J.-F. Li, "Design of reconfigurable array multipliers and multiplier-accumulators," in Proc. IEEE Asia-Pacific Conf. on Circuits and Systems (APCCAS), (Tainan), pp. 37-40, Dec. 2004.
  24. J.-F. Li,"Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs," in Proc. IEEE Asia South Pacific Design Automation Conference (ASP-DAC), (Shanghai), pp. 65-70, Jan. 2005.
  25. J.-F. Li, T.-W. Tseng, and C.-L. Wey, "An efficient transparent test scheme for word-oriented embedded memories," in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE), (Munich), pp. 574-579, Mar. 2005.
  26. J.-F. Li and C.-K. Lin, "Modeling and testing comparison faults for ternary content addressable memories," in Proc. IEEE VLSI Test Symp. (VTS), (Palm Springs), pp. 60-65, May 2005.
  27. J.-F. Li, J.-D. Yu, and Y.-J. Huang,"A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability," in Proc. IEEE International Symp. on Circuits and Systems (ISCAS), (Kobe), pp. 77-80, May, 2005.
  28. J.-F. Li and Y.-J. Huang,``An error detection and correction scheme for RAMs with partial-write function'' in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), (Taipei), pp. 115-120, Aug. 2005.
  29. C.-K. Lin, Y.-J. Huang, and J.-F. Li, "Design of low-power ternary content addressable memories with 10T cells," in Proc. 16th VLSI/CAD Symp., (Hualien), Aug. 2005.
  30. J.-F. Li and Y.-J. Huang, "A design methodology for carry lookahead adders with reconfigurability," in Proc. 16th VLSI/CAD Symp., (Hualien), Aug. 2005.
  31. J.-F. Li and C.-H. Wu, "Design-for-testability and testing of P1500 test wrapper," in Proc. 16th VLSI/CAD Symp., (Hualien), Aug. 2005.
  32. J.-F. Li,``Testing priority address encoder faults of content addressable Memories'', in Proc. IEEE Int. Test Conf. (ITC), (Austin), Paper 33.2, pp. 1-8, Nov. 2005.
  33. T.-W. Tseng, J.-F. Li, and D.-M. Chang, "A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap," in Proc.IEEE/ACM Design, Automation and Test in Europe (DATE), (Munich), pp. 53-58, Mar. 2006.
  34. C.-D. Huang, T.-W. Tseng, and J.-F. Li, "An infrastructure IP for repairing multiple RAMs in SOCs," in PRoc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. 163-166, Apr. 2006.
  35. H.-M. Shieh, C.-H. Wu, and J.-F. Li, "A multi-code compression technique for reducing system-on-chip test time," in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. 239-242, Apr. 2006.
  36. Y.-J. Huang and J.-F. Li, "Testing active neighborhood pattern-sensitive faults of ternary content addressable memories," in Proc. IEEE European Test Symposium (ETS), (Southampton, U.K.), pp. 55-60, May 2006.
  37. T.-W. Tseng, J.-F. Li, C.-C. Hsu, A. Pao, K. Chiu, and E. Chen, "A reconfigurable built-in self-repair scheme for multiple self-repairable RAMs in SOCs," in Proc. IEEE Int. Test Conf. (ITC), (Santa Clara), Paper 30.2, pp. 1-8, Oct. 2006.
  38. Y.-J. Huang, D.-M. Chang, and J.-F. Li, ``A built-in redundancy-analysis scheme for self-repairable RAMs with two-level redundancy,'' in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT) , (Arlington), pp. 362-370, Oct. 2006.
  39. J.-F. Li and C.-H. Wu, "Verification methodology for built-in self-repairable memory systems," in Proc. IEEE Asian Test Symp. (ATS), (Fukuoka), pp. 109-114, Nov. 2006.
  40. J.-D. Yu, J.-F. Li, and T.-W. Tseng,"Testing crosstalk faults of data and address buses in embedded RAMs," in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. 91-94, Apr. 2007.
  41. T.-W. Tseng, C.-H. Wu, Y.-J. Huang, J.-F. Li, Alex Pao, K. Chiu, and E. Chen,"A built-in self-repair scheme for multiport RAMs ," in Proc. IEEE VLSI Test Symp. (VTS), (Berkeley), pp. 355-360, May 2007.
  42. T.-W. Tseng, C.-H. Wu, and J.-F. Li, "Soft-error tolerant BIST scheme for random access memories ," in IEEE European Test Symposium (ETS), (Freiburg, Germany), pp.  May 2007 (informal proceeding).
  43. J.-F. Li, C.-H. Wu, and C.-S. Hou,"A reliability-enhancement technique for RAMs with dynamic faults," in Proc. 1st VLSI Test Technology Workshop (VTTW), (Hsinchu), pp. , July 2007.
  44. J.-F. Li, F. Zheng, and K.-T. Cheng,"Diagnosing scan chains using SAT-based diagnostic pattern generation," in Proc. IEEE International SOC Conference (ISOCC), (Hsinchu), pp. 273-276, Sept. 2007.
  45. Y.-X. Yang, J.-F. Li, H.-N. Liu, and C.-L. Wey,"Design of cost-efficeint memory-based FFT processors ," in Proc. IEEE International SOC Conference (ISOCC), (Hsinchu), pp. 29-32, Sept. 2007.
  46. J.-F. Li,"Testing comparison faults of ternary content addressable memories with asymmetric cells," in Proc. IEEE Asian Test Symp. (ATS), (Beijing), pp. 495-500, Oct. 2007.
  47. H.-H. Wu, J.-F. Li, C.-F. Wu, and C.-W. Wu,"CAMEL: an efficient fault simulator with coupling fault simulation enhancement for CAMs," in Proc. IEEE Asian Test Symp. (ATS), (Beijing), pp. 355-360, Oct. 2007.
  48. C.-K. Lai, Y.-J. Huang, and J.-F. Li,"A built-in self-repair scheme for ternary content addressable memories with address-input-free writing function ," in Proc. 2nd VLSI Test Technology Workshop (VTTW), (Tainan), pp. , July 2008.
  49. H.-N. Liu, Y.-J. Huang, and J.-F. Li,"A packet-based built-in self-test method for RAMs in mesh-based NoCs ," in Proc. 19th VLSI/CAD Symp., (Pintung), pp. , Aug. 2008.
  50. T.-W. Tseng and J.-F. Li, "A shared parallel built-in self-repair scheme for random access memories in SOCs," in Proc. IEEE Int. Test Conf. (ITC), (Santa Clara), Paper 25.2, pp. 1-8, Oct. 2008.
  51. Y.-J. Huang and J.-F. Li,"A low-cost pipelined BIST scheme for homogeneous RAMs in multicore chips," in Proc. IEEE Asian Test Symp. (ATS), (Sapporo), pp. 357-362, Nov. 2008.
  52. B.-W. Huang and J.-F. Li,"Efficient diagnosis algorithms for drowsy SRAMs," in Proc. IEEE Int. Symp. on Quality Electronic Design (ISQED), (San Jose), pp. 276-279, Mar. 2009.
  53. T.-W. Tseng and J.-F. Li,"Diagnosis algorithms for locating bridge defects in multi-port RAMs," in Proc. IEEE Int. Conf. on Testing and Diagnosis (ICTD), (Chengdu), pp. 1-4, April 2009.
  54. H.-N. Liu, Y.-J. Huang, and J.-F. Li, "A built-in self-repair method for RAMs in mesh-based NoCs," in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. 259-262, Apr. 2009.
  55. Y.-J. Hu, Y.-J. Huang, and J.-F. Li,"Modeling and testing comparison faults of TCAMs with asymmetric cells," in Proc. IEEE VLSI Test Symp. (VTS), (Santa Cruz), pp. 15-20, May 2009.
  56. H.-C. Lu and J.-F. Li,"A programmable online/off-line built-in self-test scheme for RAMs with ECC ", in Proc. IEEE International Symp. on Circuits and Systems (ISCAS), (Taipei), pp. 1997-2000, May, 2009.
  57. S.-P. Yong, J.-F. Li, and Y.-J. Huang,"Variability-tolerant binary content addressable memory cells," in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), (Hsinchu), pp.  44-49;, Aug. 2009.
  58. Y.-J. Hu, J.-F. Li, and Y.-J. Huang,"3-D content addressable memory architectures," in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), (Hsinchu), pp. 59-64, Aug. 2009.
  59. T.-J. Chen, T.-W. Tseng, and J.-F. Li,"A reconfigurable built-in redundnacy-analysis scheme with optimal repair efficiency for RAMs," in Proc. 3rd VLSI Test Technology Workshop (VTTW), (Nantou), pp. 93-98, July 2009.
  60. T.-J. Fu and J.-F. Li,"An embedded diagnostic data reduction scheme for RAMs with static and dynamic faults," in Proc. 20th VLSI/CAD Symp., (Hualien), pp. , August 2009.
  61. Y.-J. Huang and J.-F. Li,"Testability exploration of 3-D RAMs and CAMs," in Proc. IEEE Asian Test Symp. (ATS), (Taichun), pp. 397-402, Nov. 2009.
  62. C.-S. Hou and J.-F. Li,"Test and repair scheduling for built-in self-repair RAMs in SOCs," in Proc. IEEE Int. Symp. on Electronic Design, Test & Applications (DELTA), (Ho Chi Minh), pp. 3-7, Jan. 2010.
  63. J.-F. Li and C.-W. Wu,"Is 3D integration an opportunity or just a hype?", in Proc. IEEE Asia South Pacific Design Automation Conference (ASP-DAC), (Taipei), pp. 541-543;,Jan. 2010 (Embedded Tutorial).
  64. T.-W. Tseng, C.-S. Hou, and J.-F. Li,"Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost," in Proc. IEEE VLSI Test Symposium (VTS), (Santa Cruz) pp.  21-26, April. 2010.
  65. C.-W. Chou, Y.-J. Huang, and J.-F. Li, "Yield-enhancement techniques for 3D random acccess memroies," in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. 104-107, Apr. 2010.
  66. C.-C. Chi, C.-W. Wu, and J.-F. Li,"A low-cost and scalable test architecture for multi-core chips," in Proc. IEEE European Test Symposium (ETS), (Prague), pp. 30-35-, May 2010.
  67. Y.-J. Huang, C.-W. Chou, and J.-F. Li,"A low-cost built-in self-test scheme for an array of memories," in Proc. IEEE European Test Symposium (ETS), (Prague), pp. 75-80, May 2010.
  68. Y.-X. Chen, Y.-J. Huang, and J.-F. Li,"A memory architecture evaluation and exploration tool for 3D RAMs," in Proc. 21th VLSI/CAD Symp., (Kaohsiung), pp. , August 2010 (to appear).
  69. T.-J. Chen, T.-W. Tseng, K.-T. Wu, and J.-F. Li,"A programmable built-in self-test scheme for memories in system-in-package chips," in Proc. 3rd VLSI Test Technology Workshop (VTTW), (YiLan), pp. -, Aug. 2010.
  70. Y.-J. Huang, Y.-C. You, and J.-F. Li,"Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs ," in Proc. IEEE International SOC Conference (ISOCC), (Las Vegas), pp. 29-32, Sept. 2010.
  71. C.-W. Chou, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu,"A test integration methodology for 3D integrated circuits," in Proc. IEEE Asian Test Symp. (ATS), (Shanghai), pp. 377-382, Dec. 2010.
  72. C.-W. Chou, C.-S. Hou, and J.-F. Li, "Built-in self-diagnosis and test time reduction techniques for NAND flash memories," in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. 257-260, Apr. 2011.
  73. Y.-J. Chang, Y.-J. Huang, and J.-F. Li, "A built-in redundancy-analysis scheme for RAMs with 3D redundancy," in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. 261-264, Apr. 2011.
  74. Y.-J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu,"A built-in self-test scheme for the post-pond test of TSVs in 3D ICs," in Proc. IEEE VLSI Test Symposium (VTS), (Dana Point) pp.  20-25, May 2011.
  75. Y.-J. Huang and J.-F. Li,"Yield-enhancement techniques for homogeneous multi-core processor and memory stacked 3D ICs," in Proc. VLSI Test Technology Workshop (VTTW), (Nantou), pp. 17-22, July 2011.
  76. Y.-J. Chang, Y.-J. Huang, and J.-F. Li,"A BIRA scheme with optimal repair rate for large RAMs with 3D redundancy," in Proc. 22th VLSI/CAD Symp., (YunLin), pp. 360-363, Aug. 2011.
  77. C.-W. Chou, J.-F. Li, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "Hierarchical test integration methodology for 3D integrated circuits," in Proc. 22th VLSI/CAD Symp. , (YunLin), pp. 372-375, Aug. 2011.
  78. C.-W. Wu, S.-K. Lu, and J.-F. Li,"On test and repair of 3D random access memory", in Proc. IEEE Asia South Pacific Design Automation Conference (ASP-DAC), (Sydney), pp. 744-749, Jan. 2012 (invited paper).
  79. C.-W. Chou and J.-F. Li, "A TSV-defect-tolerance test interface for 3D ICs," in Digest of 3D Integration Workshop of IEEE/ACM Design, Automation and Test in Europe (DATE), (Dresden), pp. -, Mar. 2012.
  80. H.-Y.Wu, C.-W. Chou, and J.-F. Li, "A built-in delay measurement method for TSVs," in Digest of 3D Integration Workshop of IEEE/ACM Design, Automation and Test in Europe (DATE), (Dresden), pp. -, Mar. 2012.
  81. Y.-X. Chen, Y.-J. Huang, and J.-F. Li,"Test cost optimization technique for the pre-bond test of 3D ICs," in Proc. IEEE VLSI Test Symposium (VTS), (Hawaii) pp. 102-107, April 2012.
  82. L.-J. Chang, Y.-J. Huang, and J.-F. Li, "Area and reliability efficient ECC scheme for 3D RAMs," in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. 1-4, Apr. 2012.
  83. Y.-J. Huang, J.-F. Li, and C.-W. Chou "Post-bond test techniques for TSVs with crosstalk faults in 3D ICs," in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. 1-4, Apr. 2012.
  84. C.-S. Hou and J.-F. Li,"Disturbance fault analysis and testing on various NAND flash memories," in Proc. IEEE European Test Symposium (ETS), (Annecy), pp. , May 2012.
  85. C.-S. Hou, J.-F. Li, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "A FPGA-based platform for testing and analyzing date retention time of DRAMs," in Proc. VLSI Test Technology Workshop (VTTW), (YiLan), pp. -, July 2012.
  86. H.-Y. Wu, C.-W. Chou, and J.-F. Li,"A built-in delay measurement method for the TSVs in 3D ICs," in Proc. 23th VLSI/CAD Symp., (Pintung), pp. -, Aug. 2012.
  87. Y.-C. Yu, C.-W. Chou, J.-F. Li, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "A built-in self-test scheme for 3D RAMs," in Proc. IEEE Int. Test Conf. (ITC), (Anaheim), Paper 14.4, pp. 1-9, Nov. 2012.
  88. C.-S. Hou, J.-F. Li, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu "An FPGA test platform for analyzing data retention time distribution of DRAMs," in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. 225-228, Apr. 2013.
  89. Y.-C. Yu, C.-S. Hou, L.-J. Chang, J.-F. Li, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "A hybrid ECC and redundancy technique for reducing refresh power of DRAMs," in Proc. IEEE VLSI Test Symposium (VTS), (Berkeley), pp.  208-213, April 2013.
  90. C.-S. Hou and J.-F. Li,"Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs," in Proc. IEEE VLSI Test Symposium (VTS), (Berkeley) pp.  270-275, April 2013.
  91. J.-F. Li, C.-W. Wu, M. Aoyagi, M.-F. Chang, and D.-M. Kwai, "Special session 4C: Hot topic 3D-IC design and test," in Proc. IEEE VLSI Test Symposium (VTS), (Berkeley), pp. 1-1, April 2013.
  92. C.-S. Hou and J.-F. Li,"High repair-efficiency BISR scheme for RAMs by reusing bitmap for bit redundancy," in Proc.VLSI Test Technology Workshop (VTTW), (New Taipei) pp. -,July 2013.
  93. C.-W. Chou, C.-S. Hou, C.-C. Yang, and J.-F. Li,"A TSV-defect-tolerance test interface for 3D ICs," in Proc. 24th VLSI/CAD Symp., (Kaohsiung), pp. -, Aug. 2013.
  94. C.-M. Chang, C.-S. Hou, and J.-F. Li,"A test method for classifying refresh periods of multiple-refresh-period DRAMs," in Proc. 24th VLSI/CAD Symp., (Kaohsiung), pp. -, Aug. 2013.
  95. C.-C. Yang, C.-W. Chou, and J.-F. Li,"A TSV repair scheme using enhanced test access architecture for 3-D ICs," in Proc. IEEE Asian Test Symp. (ATS), (Yilan), pp. -, Nov. 2013.
  96. C.-S. Hou and J.-F. Li,"Testing disturbance faults in various NAND flash memories," in Proc. IEEE Asian Test Symp. (ATS), (Yilan), pp. -, Nov. 2013.
  97. Y.-X. Chen and J.-F. Li,"Testing backup and restore faults of non-volatile logic-based system chips using BIST method," in Proc.VLSI Test Technology Workshop (VTTW), (Taichung) pp. -, July 2014.
  98. C.-S. Hou and J.-F. Li,"Built-in self-repair scheme for eDRAMs with physical and logical reconfigurable redundancies," in Proc.VLSI Test Technology Workshop (VTTW), (Taichung) pp. -,July 2014
  99. Y.-H. Chen, C.-S. Hou, and J.-F. Li,"Transparent BIST for RAMs using BCH for data integrity checking," in Proc. 25th VLSI/CAD Symp., (Taichung), pp. -, Aug. 2014.
  100. W.-H. Yang, C.-S. Hou, and J.-F. Li,"A BIST scheme for testing TSVs of logic-DRAM stacks," in Proc. 25th VLSI/CAD Symp., (Taichung), pp. -, Aug. 2014.
  101. I. H.-R. Jiang, N. Viswanathan, T.-C. Chen, and J.-F. Li,"The overview of 2014 CAD contest at ICCAD," in Proc.of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (San Jose), pp. -, Nov. 2014.
  102. Y.-C. Yu, C.-C. Yang, J.-F. Li, C.-Y. Lo, C.-H. Chen, J.-S. Lai, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu,"BIST-assisted tuning scheme for minimizing IO-channel power of TSV-based 3D DRAMs," in Proc. IEEE Asian Test Symp. (ATS), (Hangzhou), pp. -, Nov. 2014.
  103. K.-T. Wu, J.-F. Li, Y.-C. Yu, C.-S. Hou, C.-C. Yang, D.-M. Kwai, Y.-F. Chou, and C.-Y. Lo,"Intra-channel reconfigurable interface for TSV and micro bump fault tolerance in 3D DRAMs," in Proc. IEEE Asian Test Symp. (ATS), (Hangzhou), pp. -, Nov. 2014.
  104. Y.-X. Chen and J.-F. Li,"Testing of non-volatile logic-based system chips," in Proc. IEEE Asian Test Symp. (ATS), (Hangzhou), pp. -, Nov. 2014.
  105. Y.-X. Chen and J.-F. Li,"Fault modeling and testing of 1T1R memristor memories," in Proc. IEEE VLSI Test Symposium (VTS), (Napa) pp.  -, April 2015.
  106. C.-C. Yang, J.-F. Li, Y.-C. Yu, K.-T. Wu, C.-Y. Lo, C.-H. Chen, J.-S. Lai, D.-M. Kwai, and Y.-F. Chou,"A hybrid built-in self-test scheme for DRAMs," in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), (Hsinchu), pp. -, Apr. 2015 (Best Paper Award Candidate).
  107. T.-H. Li, J.-F. Li, and Y.-X. Chen, "Fusing methodology of multi-time BISR for RAMs in SOCs," in Proc.VLSI Test Technology Workshop (VTTW), (Taichung) pp. -,July 2015
  108. C.-W. Chou, J.-F. Li, and Y.-X. Chen, "Low-pin-count BIST scheme for RAMs in 3D ICs," in Proc. 26th VLSI/CAD Symp., (Taichung), pp. -, Aug. 2015.
  109. C.-W. Chou, Y.-X.Chen, and J.-F. Li,"Testing inter-word coupling faults of wideIO DRAMs," in Proc. IEEE Asian Test Symp. (ATS), (Mumbai), pp. -, Nov. 2015 (to appear).
  110. R.-L. M. Wang, Y.-C. Yu, J.-F. Li, "Design considerations of 3D stacked DRAM caches," 1st International Workshop on Emerging Memory Solutions, (Dresden) , March 2016.
  111. Y.-X. Chen and J.-F. Li,"Architecture evaluation tool for 3D CAMs,"1st International Workshop on Emerging Memory Solutions, (Dresden) March 2016 .
  112. Y.-T. Li, Y.-X. Chen and J.-F. Li,"Fault modeling and testing of resistive nonvolatile 8T-SRAMs," in Proc. IEEE VLSI Test Symposium (VTS), (Las Vegas) pp.  -, April 2016.
  113. H.-Y. Wu, Y.-X. Chen, and J.-F. Li,"A built-in method for measuring the delay of TSVs in 3D ICs," in Proc. IEEE European Test Symposium (ETS), (Amsterdam), pp. -, May 2016.
  114. T.-Y. Lin, Y.-X. Chen, J.-F. Li, C.-Y. Lo, D.-M. Kwai. and Y.-F. Chou, "Test and DFT techniques for identifying boundary currents of memristor memories," in Proc.VLSI Test Technology Workshop (VTTW), (Nantou) pp. -,July 2016
  115. Y.-T. Li, Y.-X. Chen, and J.-F. Li, "A march-like diagnosis test for Rnv8T SRAMs," in Proc. 27th VLSI/CAD Symp., (Kaohsiung), pp. -, Aug. 2016.
  116. C.-S. Hou, Y.-X. Chen, J.-F. Li, C.-Y. Lo, D.-M. Kwai, and Y.-F. Chou, "A built-in self-repair scheme for DRAMs with spare rows, columns, and bits," in Proc. IEEE Int. Test Conf. (ITC), (Austin), Paper, pp. -, Nov. 2016.
  117. T.-Y. Lin, Y.-X.Chen, J.-F. Li, C.-Y. Lo, D.-M. Kwai, and Y.-F. Chou,"A test method for finding boundary curents of 1T1R memristor memories," in Proc. IEEE Asian Test Symp. (ATS), (Hiroshima), pp. -, Nov. 2016.
  118. C.-M. Chang, Y.-X. Chen, and J.-F. Li,"A built-in self-test scheme for classifying refresh period of DRAMs," in Proc. IEEE European Test Symposium (ETS), (Cyprus), pp. -, May 2017.
  119. T.-F. Hsieh, J.-F. Li, K.-T. Wu, J.-S. Lai, C.-Y. Lo, D.-M. Kwai, and Y.-F. Chou, "Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs," in Proc. IEEE Int. Test Conf. in Asia (ITC-Asia), (Taipei), Paper, pp. -, Sept. 2017.
  120. K.-T. Wu, J.-F. Li, C.-Y. Lo, J.-S. Lai, D.-M. Kwai, and Y.-F. Chou, "A channel-sharable built-in self-test scheme for multi-channel DRAMs", in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2018), (Jeju Island), pp.   - , Jan. 2018.
  121. Y-J.Hu, T. Wu, Y.-C. Chung, and J.-F. Li, "A 3-D priority address encoder for 3-D content addressable memories," 3st International Workshop on Emerging Memory Solutions, (Dresden) , March 2018.
  122. L.-W. Deng, J.-F. Li, and Y.-X. Chen,"Modeling and testing comparison faults of memristive ternary content addressable memories " in Proc. IEEE European Test Symposium (ETS), (Bremen), pp. -, May 2018.
  123. Y.-T. Li, J.-F. Li, C.-L. Hsu, and C.-T. Sun, "Diagnosis of resistive nonvolatile-8T SRAMs", in Proc. International SoC Design Conference (ISOCC), (Daegu), pp.   -, Nov. 2018.
  124. T.-L. Tsai, J.-F. Li, C.-L. Hsu, and C.-T. Sun, "Testing stuck-open faults of priority address encoder in content addressable memories", in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) , (Tokyo), pp.   - , Jan. 2019.
  125. H.-C. Chen, J.-F. Li, C.-L. Hsu, and C.-T. Sun,"Configurable 8T SRAM for enabling in-memory computing ", in Proc. International Conference on Communication Engineering and Technology (ICCET) , (Nagoya), pp.   -, April 2019.
  126. T.-L. Tsai, J.-F. Li, C.-L. Hsu, and C.-T. Sun, "Testing of in-memory-computing 8T SRAMs", in Proc. IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) , (Leiden/Delft), pp.   -, Oct. 2019 (Outstanding student paper award).
  127. W.-H. Yang, J.-F. Li, C.-L. Hsu, C.-T. Sun, and S.-H. Huang, "A built-in self-test scheme for TSVs of logic-DRAM stacked 3D ICs", in Proc. IEEE International 3D Systems Integration Conference (3DIC) , (Sendai), pp.   -, Oct. 2019.
  128. F.-H. Tang, H.-Y. Kao, S.-H. Huang, and J.-F. Li, "3D test wrapper chain optimization with I/O cells binding considered, in Proc. IEEE International 3D Systems Integration Conference (3DIC) , (Sendai), pp.   -, Oct. 2019.
  129. T.-F. Hsieh, J.-F. Li, K.-T. Wu, J.-S. Lai, C.-Y. Lo, D.-M. Kwai, and Y.-F. Chou, "Refresh power reduction of DRAMs in DNN systems using hybrid voting and ECC method," in Proc. IEEE Int. Test Conf. in Asia (ITC-Asia), (Taipei), Paper, pp. -, Sept. 2020
  130. J.-F. Li, T.-L. Tsai, C.-L. Hsu, and C.-T. Sun, "Testing of configurable 8T SRAMs for in-memory computing", in Proc. IEEE Asian Test Symposium (ATS) , (Malaysia), pp.   -, Nov. 2020.
  131. Y.-Y. Tsai and J.-F. Li, "Evaluating the impact of fault-tolerance capability of deep neural networks caused by faults", in Proc. IEEE Int'l System-on-Chip Conference (SOCC), (Las Vegas), pp.   -, Sept. 2021.
  132. W. Chang, Y.-G. Chen, P.-Y. Huang, and J.-F. Li, "An aging-aware CMOS SRAM structure design for boolean logic in-memory computing", in Proc. IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) , (Athens), pp.   -, Oct. 2021.
  133. Y.-C. Yang and J.-F. Li, "Fault modeling and testing for RRAM-based computing-in-memories," in Proc. IEEE Int. Test Conf. in Asia (ITC-Asia), (Taipei), Paper, pp. -, Aug. 2022.
  134. J.-F. Li, "Testing and reliability of computing-in memories: solutions and challenges," in Proc. IEEE Int. Test Conf. in Asia (ITC-Asia), (Taipei), Paper, pp. -, Aug. 2022.
  135. Z.-W. Pan and J.-F. Li, "DFT-enhanced test scheme for spin-transfer-torque (STT) MRAMs," in Proc. IEEE Int. Test Conf. (ITC), (Anaheim), Paper, pp. , Sept. 2022
  136. C.-H. Cheng, S.-H. Huang, and J.-F. Li, "Design and dataflow for multibit SRAM-based MAC operations", in Proc. International SoC Design Conference (ISOCC), (Gangwon-do), pp.   -, Oct. 2022.
  137. J.-F. Li, "Design and test of computing-in memories ", in Proc. International SoC Design Conference (ISOCC), (Gangwon-do), pp.   -, Oct. 2022.
  138. Y.-G. Chen, P-Y. Huang, and J.-F. Li, "An on-line aging detection and tolerance framework for improving reliability of STT-MRAMs", in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) , (Tokyo), pp.   - , Jan. 2023.
  139. M.-S. Wu, Y.-L. Chua, J.-F. Li, Y.-T. Chuan, and S.-H. Huang, "Fault-aware ECC scheme for enhancing the read reliability of STT-MRAMs," in Proc. IEEE Int. Test Conf. in Asia (ITC-Asia), (Matsue), Paper, pp. -, Sept. 2023.
  140. S.-H. Huang, W.-C. Cheng, and J.-F. Li,"Hardware trojans of computing-in-memories: issues and methods", in Proc. IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) , (Juan-Les-Pins), pp.   -, Oct. 2023.
  141. J.-F. Li,"Testing of computing-in-memories: faults, test algorithms, and design-for-testability", in Proc. IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) , (Juan-Les-Pins), pp.   -, Oct. 2023.
  142. P.-Y. Lin and J.-F. Li,"Parallel-check trimming test approach for selecting the reference resistance of STT-MRAMs " in Proc. IEEE European Test Symposium (ETS), (Hague), pp. -, May 2024.
  143. J.-F. Li,"Testing of digital computing-in memories with MAC function", in Proc. IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) , (Oxfordshire), pp.   -, Oct. 2024.
  144. Y.-C. Huang, P.-Y. Lin, J.-F. Li, H.-S. Fu, and Y.-P. Lee, "Efficient built-in self-test scheme for inter-die interconnects of chiplet-based chips," in Proc. IEEE Int. Test Conf. (ITC), (San Diego), Paper, pp. , Nov. 2024
  145. Y.-T. Chuan, L.-Y. Su, S.-H. Huang, and J.-F. Li, "Behavioral model compiler for simulating read disturbances and read/write errors in STT-MRAMs," in Proc. IEEE Int. VLSI Symp. on Technology, Systems, and Applications, (Hsinchu), Paper, pp. , April 2025 (Best paper award candidates)
  146. P.-Y. Lin and J.-F. Li,"Local trimming method for enhancing the read reliability of STT-MRAMs" in Proc. IEEE European Test Symposium (ETS), (Tallinn), pp. -, May 2025 (accepted).
  147. C.-L. Hsiao, H.-W. Chen, S.-H. Huang and J.-F. Li,"A machine learning-based power prediction framework for DCIM circuits", in Proc. IEEE Symp. on Low Power and High-Speed Chips and Systems (COOL Chips 28), (Tokyo), pp.  -, April 2025. (Best Poster Award)

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• PATENTS

  1. C.-F. Wu, C.-W. Wang, J.-F. Li, C.-W. Wu, C.-C. Teng, and C.-K. Chiu,``Built-in programmable self-diagnostic circuit for SRAM unit'', U.S. Patent, No.6459638, Oct. 2002, (Claiming diagnostic method).
  2. C.-F. Wu, C.-W. Wang, J.-F. Li, C.-W. Wu, C.-C. Teng, and C.-K. Chiu, ``Built-in programmable self-diagnostic circuit for SRAM unit'', U.S. Patent, No. 6529430, Mar. 2003, (Claiming diagnostic circuit).
  3. C.-F. Wu, C.-W. Wang, J.-F. Li, C.-W. Wu, C.-C. Teng, and C.-K. Chiu, ``Built-in programmable self-diagnostic method and circuit for SRAM'', R.O.C. Patent, No. 169346, Apr. 2003, (in Chinese).
  4. T.-W. Tseng, Y.-J. Huang, C.-H. Wu, J.-F. Li, A. Pao, C.-K. Chiu, and E. Chen, ``Circuit and method for built-in self-repair of a multiport memory thereof'', U.S. Patent, No. 7596728, 2009.
  5. T.-W. Tseng, C.-C. Hsu, J.-F. Li, A. Pao, C.-K. Chiu, and E. Chen, ``Built-in redundancy analyzer and method for redundancy analysis'', R.O.C. Patent, No. I326453, 2010, (in chinese).
  6. T.-W. Tseng, C.-C. Hsu, J.-F. Li, A. Pao, C.-K. Chiu, and E. Chen, ``Built-in redundancy analyzer and method for redundancy analysis'', U.S. Patent, No. 7779312, 2010.
  7. T.-W. Tseng, Y.-J. Huang, C.-H. Wu, J.-F. Li, A. Pao, C.-K. Chiu, and E. Chen, ``Circuit and method for built-in self-repair of a multiport memory'', R.O.C. Patent, No. I332665, 2010, (in chinese).
  8. D.-M. Kwai, C.-Y. Lo, J.-F. Li, C.-W Chou, and Y.-C. Yu, ``3-D memory and built-in self-test circuit thereof'', R.O.C. patent, No. I459008, 2014.
  9. C.-Y. Lo, D.-M. Kwai, J.-F. Li, Y.-C. Yu, and C.-S. Hou, ``Hybrid error repair method and memory apparatus thereof,", R.O.C. patent, No. I502601, 2015, (in Chinese).
  10. D.-M. Kwai, C.-Y. Lo, J.-F. Li, C.-W Chou, and Y.-C. Yu, ``3-D memory and built-in self-test circuit thereof'', USA. patent, No., 9406401, 2016.
  11. C.-Y. Lo, D.-M. Kwai, C.-C. Yang, K.-T. Wu, Y.-C. Yu, and J.-F. Li, "Fault-tolerance through silicon via interface and controlling method thereof'', R.O.C. patent, No. I556247, 2016, (in Chinese).
  12. C.-Y. Lo, D.-M. Kwai, C.-C. Yang, K.-T. Wu, Y.-C. Yu, and J.-F. Li, "Fault-tolerance through silicon via interface and controlling method thereof'', USA. patent, No. 9588717, 2017.
  13. J.-F. Li, H.-Y. Wu, C.-W. Chou, Y.-X. Chen, "Delay measurement circuit and mesuring method thereof'', R.O.C. patent, No. I585427. 2017.
  14. K.-T. Wu, J.-S. Lai, C.-Y. Lo, and J.-F. Li, "Memory control circuit and memory test method", R.O.C. patent, No. I620190, 2018 (in Chinese)
  15. J.-F. Li, H.-Y. Wu, C.-W. Chou, Y.-X. Chen, "Delay measurement circuit and mesuring method thereof'', USA. patent, No.10209298. Feb. 2019.
  16. K.-T. Wu, J.-S. Lai, C.-Y. Lo, and J.-F. Li, "Memory control circuit and memory test method", USA patent, No. 10311964. June 2019.
  17. J.-F. Li and Z.-W. Pan," Memory device reference resistance trimming method and memory device", R. O. C. patent, (patent pending) 2023.
  18. J.-F. Li, M.-S. Wu, Y.-L. Chua, S.-H. Huang, and Y.-T. Chuan"Error correction system and method for STT-MRAMs", R.O.C. patent, (patent pending), 2024.

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• JOURNAL PAPERS (In Chinese)

  1. C.-W. Wang, C.-F. Wu, J.-F. Li, R.-F. Huang, and C.-W. Wu,``A built-in self-test and self-diagnosis scheme for embedded SRAM'', IC Design Magazine, vol. 1, no. 12, pp. 1-17, Dec. 2002, (in Chinese).
  2. J.-F. Li, ``Testing and diagnosing RAM faults and comparison faults of binary content addressable memories'', IC Design Magazine, pp. , Jan. 2005, (in Chinese, invited paper).
  3. B.-W. Huang, D.-M. Kwai, and J.-F. Li, ``Introduction to IEEE P1687 (IJTAG) test standard", SOC Technical Journal, STC, ITRI, pp. 17-24, Dec. 2009, (in Chinese).
  4. Y.-J. Huang, J.-F. Li, and T.-W. Tseng, ``A built-in self-test scheme for the post-bond test of TSVs in 3-D ICs", Information and Communications Research LaboratoriesTechnical Journal, pp. -, Oct. 2011, (in Chinese).
  5. C.-Y. Lo, C.-W. Chou, and J.-F. Li, ``A test interface design for 3-D IC applications", Information and Communications Research LaboratoriesTechnical Journal, pp. -, Oct. 2011, (in Chinese).
  6. K.-T. Wu, Y.-C. Yu, D.-M. Kwai, Y.-F. Chou, Jin-Fu Li, and C.-Y. Lo,"Intra-channel reconfigurable interface for TSV and micro bump fault tolerance in 3D DRAMs," in Information and Communications Research LaboratoriesTechnical Journal, pp. 74-84, Dec. 2014 (in Chinese) D
  7. Y.-T. Li, Y.-X. Chen, J.-F. Li, K.-T. Wu, C.-Y. Lo, D.-M. Kwai, and Y.-F. Chou,"Modeling, testing, and diagnosis of memristor-related faults in resistive nonvolatile-8T SRAMs," in Information and Communications Research LaboratoriesTechnical (ICL) @Journal, pp. 100-108, Nov. 2016 (in Chinese) E

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