Publications

Publications

Journal Papers:
1. S.-W. Tu, W.-Z. Shen, Y.-W. Chang, T.-C. Chen, and J.-Y. Jou, ``Inductance modeling for on-chip interconnects," in International Journal of Analog Integrated Circuits and Signal Processing, Vol. 35, No. 1, pp. 65--78, April 2003. (invited paper) (SCI, EI)
2. T.-C. Chen, S.-R. Pan, and Y.-W. Chang, ``Timing modeling and optimization under the transmission line model," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), Vol. 12, No. 1, pp. 28--41, Jan. 2004. (SCI, EI)
3. T.-C. Chen and Y.-W. Chang, ``Multilevel full-chip gridless routing with applications to optical-proximity correction," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 6, pp. 1041--1053, June 2007. (SCI, EI)
4. T.-C. Chen, G.-W. Liao, and Y.-W. Chang, ``Predictive formulae for OPC with applications to lithography-friendly routing," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 1, pp. 40--50, Jan. 2010. (SCI, EI)
ACM/IEEE Conference Papers:
1. T.-C. Chen, S.-R. Pan, and Y.-W. Chang, ``Performance optimization by wire and buffer sizing under the transmission line model," in Proceedings of IEEE International Conference on Computer Design (ICCD-01), pp. 192--197, Austin, TX, USA, Sep. 2001.
2. S.-W. Tu, W.-Z. Shen, Y.-W. Chang, and T.-C. Chen, ``Inductance modeling for on-chip interconnects," in Proceedings of IEEE Symposium on Circuits and Systems (ISCAS-2002), vol. 3, pp. 787--790, Pheonix, AZ, USA, May 2002.
3. T.-C. Chen and Y.-W. Chang, ``Multilevel gridless full-chip routing considering optical proximity correction," in Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC-2005) , pp. 1160--1163, Shanghai, China, Jan. 2005.
4. T.-C. Chen, Y.-W. Chang, and S.-C. Lin, ``A novel framework for multilevel full-chip gridless routing," in Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC-2006) , pp. 636--641, Yokohama, Japan, Jan. 2006.
5. C.-W. Lin, M.-C. Tsai, K.-Y. Lee, T.-C. Chen, T.-C. Wang, and Y.-W. Chang, ``Recent research and emerging challenges in physical design for manufacturability/reliability," in Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC-2007) , pp. 238--243, Yokohama, Japan, Jan. 2007. (invited paper)
6. T.-C. Chen, G.-W. Liao, and Y.-W. Chang, ``Predictive formulae for OPC with applications to lithography-friendly routing," in Proceedings of ACM/IEEE Design Automation Conference (DAC-2008) , pp. 510--515, Anaheim, CA, USA, June 2008. (Best Paper Nominee; received the highest score in the Physical Design & Manufacturability track)
7. C.-J. Chang, P.-J. Huang, T.-C. Chen, and C.-N. Jimmy Liu, ``ILP-Based Inter-Die Routing for 3D ICs," in Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC-2011) , pp. 330--335, Yokohama, Japan, Jan. 2011.
8. T.-C. Chen, T.-H. Li, B.-T. Lai, and Y.-C. Tsai, ``Recent Research Development in Physical Design for Manufacturability," in Proceedings of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS-2011) , pp. Tp2E-3, Seoul, Korea, Aug. 2011.
9. T.-H. Li, W.-C. Chen, X.-T. Cai, and T.-C. Chen, ``Escape Routing of Differential Pairs Considering Length Matching," in Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC-2012) , pp. 139--144, Sydney, Australia, Jan. 2012.
10. T.-Y. Kuan, Y.-C. Chang, and T.-C. Chen, ``Micro-Bump Assignment for 3D ICs using Order Relation," in Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC-2012) , pp. 341--346, Sydney, Australia, Jan. 2012.
11. Bi-Ting Lai, Tai-Hung Li, and Tai-Chen Chen, ``Native-Conflict-Avoiding Track Routing for Double Patterning Technology," in Proceedings of IEEE International SOC Conference (SOCC-2012) , pp. 381--386, Niagara Falls, NY, USA, Spe. 2012.
12. Yun-Chih Tsai, Tai-Hung Li, Tai-Chen Chen, and Chung-Wei Yeh, ``Electromigration- and Obstacle-Avoiding Routing Tree Construction," in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test (VLSIDAT-2013) , pp. 1--4, Hsinchu, Taiwan, Apr. 2013.
13. Yan-Wun Wang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu, ``Simultaneous Hotspot Temperature and Supply Noise Reductions using Thermal TSVs and Decoupling Capacitors," in Proceedings of IEEE Asia Symposium on Quality Electronic Design (ASQED-2013) , pp. 245--248, Penang, Malaysia, Aug. 2013.
Other Conference Papers:
1. S.-W. Tu, W.-Z. Shen, Y.-W. Chang, and T.-C. Chen, ``Inductance modeling for on-chip interconnects," in Proceedings of The 12th VLSI Design/CAD Symposium, Hsinchu, Taiwan, Aug. 2001.
2. T.-C. Chen, S.-F. Chen, and Y.-W. Chang, ``Multilevel full-chip gridless routing," in Proceedings of The 15th VLSI Design/CAD Symposium, Pingdong, Taiwan, Aug. 2004.
3. T.-C. Chen and Y.-W. Chang, ``Full-chip gridless routing using a novel multilevel framework," in Proceedings of The 16th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2005.
4. T.-C. Chen, G.-W. Liao, and Y.-W. Chang, ``Lithography-aware routing with predictive OPC formulae," in Proceedings of The 18th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2007.
5. C.-J. Chang, P.-J. Huang, T.-Y. Kuan, Y.-W. Wang, T.-C. Chen, and C.-N. Jimmy Liu, ``Inter-die routing for 3-D stacked ICs," in Proceedings of The 21th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2010.
6. T.-Y. Kuan, C.-Y. Lee, C.-F. Lin, Y.-C. Chang, C.-H. Hsieh, and T.-C. Chen, ``Micro-Bump Assignment for 3D ICs using Order Relation," in Proceedings of The 22th VLSI Design/CAD Symposium, Yunlin, Taiwan, Aug. 2011.
7. Bi-Ting Lai, Quo-Ting Liu, Jun-Lin Huang, and Tai-Chen Chen, ``Native-Conflict-Avoiding Track Routing for Double Patterning Technology," in Proceedings of The 23th VLSI Design/CAD Symposium, Pingdong, Taiwan, Aug. 2012.
8. Tai-Hung Li, Pei-Yu Lee, Chin-Yaw Chen, and Tai-Chen Chen, ``ILP-Based Escape Routing for Length-Matching Differential Pairs," in Proceedings of The 23th VLSI Design/CAD Symposium, Pingdong, Taiwan, Aug. 2012. (Best Paper Nominee)
U.S. Patents:
1. S.-C. Lin, T.-C. Chen, Y.-W. Chang, and F.-Y. Chang, "V-shaped multilevel full-chip gridless routing," U.S. Patent, No. 7,707,536 (Technology transferred to SpringSoft Inc. [思源科技]; patent application filed by SpringSoft), issued on April 27, 2010.
Technical Report:
1. T.-C. Chen and Y.-W. Chang, ``Challenges in physical design," Component Magazine, pp. 68--74, June 2003. (invited article)
Thesis/Dissertation:
1. T.-C. Chen, ``Performance Optimization Under the Transmission Line Model," Master Thesis, National Chiao Tung University, June 2001.
2. T.-C. Chen, ``Multilevel Gridless Full-Chip Routing Considering Performance and Manufacturability," Ph.D. Dissertation, National Taiwan University, June 2007.

Last update: 2012/09/20