歡迎光臨 蔡曜聰教授 個人網頁
(Device Modeling Laboratory.元件模擬實驗室)

yttsai's photo

基本資料:

Biography:

Yao-Tsung Tsai received the B.S. degree in electrical engineering from National Taiwan University of Science and Technology, Taiwan, in 1982, the M.S. degree in electronics engineering from National Chiao Tung University, Taiwan, in 1984, and the Ph.D. degree in electrical engineering from Michigan State University, East Lansing, in 1990. In 1990, he joined the Department of Electrical Engineering at National Central University, Taiwan, as an Associate Professor and currently he is a Professor. His research interests include the areas of device simulation, circuit simulation, and high-speed computation.

主要學歷:
•美國密西根州立大學電機工程研究所博士 1986.09-1990.06
•國立交通大學 電子工程研究所碩士 1982.09-1984.06
•國立臺灣科技大學 電機工程學系 學士 1980.09-1982.06
現職與經歷:
•現職：中央大學 電機工程學系　教授
•經歷：
.中央大學 電機工程學系　教授 1998.08-迄今
.中央大學 電機工程學系　副教授1990.08-1998.07
專長:
•半導體元件(Semiconductor devices)
•元件模擬(Device simulation)
•電路模擬(Circuit simulation)
•程式設計(Programming in C)
研究方向:
•Semiconductor Device Modeling and Simulation
論文著作:
(A) Journal Papers:

  1. Feng-Tso Chien, Chii-Wen Chen, Chien-Nan Liao, Tien-Chun Lee, Chi-Ling Wang, Ching-Hwa Cheng, Hsien-Chin Chiu, and Yao-Tsung Tsai, “A Novel Self-Aligned Raised Source/Drain Poly-Silicon Thin-Film Transistor with a High-Current Structure,” IEEE Electron Device Letters, Vol. 32, No. 8, pp. 1080-1082, 2011. (SCI)

  2. Feng-Tso Chien, Chien-Nan Liao, Chin-Mu Fang, and Yao-Tsung Tsai, “High-Performance Double-Channel Poly-Silicon Thin-Film Transistor with Raised Drain and Reduced Drain Electric Field Structures,” IEEE Trans. Electron Devices, Vol. 56, No. 3, pp. 441-447, 2009. (SCI)

  3. Chi-Hon Ho, Chien-Nan Liao, Feng-Tso Chien, and Yao-Tsung Tsai, “Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer,” Chinese Physics Letters, Vol. 26, No. 1, pp. 017303-1 - 017303-4, 2009. (SCI)

  4. Chi-Hon Ho, Chia-Cherng Chang, Szu-Ju Li, and Yao-Tsung Tsai, “The Branch-Cut Method and Its Applications in Two-Dimensional Device Simulation,” ACTA International Journal of Modelling and Simulation, Vol. 20, No. 1, pp. 1-6, 2009. (EI)

  5. Feng-Tso Chien, Chin-Mu Fang, Chien-Nan Liao, Chii-Wen Chen, Ching-Hwa Cheng, and Yao-Tsung Tsai, “A Novel High-Performance Poly-Silicon Thin-Film Transistor with a Double-Channel Structure,” IEEE Electron Device Letters, Vol. 29, No. 11, pp. 1229-1231, 2008. (SCI)

  6. Chi-Hon Ho, Jun-Yi Pon, and Yao-Tsung Tsai, “The Branch-Cut Method and Its Application to Partially Depleted SOI MOSFET Simulation for Kink Effect Definition,” Journal of the Chinese Institute of Engineers, Vol. 31, No. 7, pp. 1219-1224, 2008.(SCI)

  7. Chi-Hon Ho, Chien-Nan Liao, Feng-Tso Chien, and Yao-Tsung Tsai, “An Analytical model for SOI RESURF Lateral Double Diffused Metal-Oxide-Semiconductor Field Effect Transistor Devices with SIPOS shielding layer,” Japanese Journal of Applied Physics, Vol. 47, No. 7, pp. 5369-5373, 2008. (SCI)

  8. Chi-Hon Ho, Chien-Nan Liao, Feng-Tso Chien, and Yao-Tsung Tsai, “Computer-Aided Evolution for Solving the Analytic Kronig-Penny Model,” Journal of the Chinese Institute of Engineers, Vol. 31, No. 1, pp. 121-125, 2008. (SCI, NSC 95-2516-S-008-001)

  9. Feng-Tso Chien, Chien-Nan Liao, Jin-Mu Yin, Hsien-Chin Chiu, and Yao-Tsung Tsai, “Device linearity improvement of In0.49Ga0.51P/In0.15Ga0.85As doped-channel FETs with a metal plug alloy process,” Semiconductor Science and Technology, Vol. 23, pp. 1-5, 2008. (SCI, NSC 96-2213-E-035-021)

  10. Chien-Nan Liao, Feng-Tso Chien, Chii-Wen Chen, and Yao-Tsung Tsai, “Study of Drain Alloy for Antimony Substrate Vertical High Voltage Power Metal Oxide Semiconductor Field Effect Transistors,” Japanese Journal of Applied Physics, Vol. 47, No. 4, pp. 2122-2123, 2008. (SCI)

  11. Feng-Tso Chien, Chien-Nan Liao, Chi-Ling Wang, Hsien-Chin Chiu, and Yao-Tsung Tsai, “Low On-Resistance Trench Power MOSFETs Design,” Electronics Letters, Vol. 44, No. 3, 2008. (SCI)

  12. Szu-Ju Li, Chi-Hon Ho, Chien-Nan Liao, and Yao-Tsung Tsai, “Log-Scale Method with Equivalent Circuit Model in Semiconductor Device Simulations,” Journal of the Chinese Institute of Engineers, Vol. 30, No. 5, pp. 843-846, 2007. (SCI, NSC 95-2516-S-008-001)

  13. Szu-Ju Li, Chi-Hon Ho, and Yao-Tsung Tsai, “Kronig-Penney Model Simulation with Equivalent Circuit Method,” International Journal of Numerical Modelling-Electronic Networks Devices and Fields, Vol. 20, pp. 109-116, 2007. (SCI, NSC 94-2516-S-008-002)

  14. Szu-Ju Li, Jing-Fu Dai, Chia-Cherng Chang, Chau-Hsin Huang, and Yao-Tsung Tsai, “Development of 3-D equivalent-circuit modeling with decoupled L-ILU factorization in semiconductor device simulation,” International Journal of Numerical Modelling-Electronic Networks Devices and Fields, Vol. 20, pp. 133-148, 2007. (SCI, NSC 94-2516-S-008-002)

  15. Chia-Cherng Chang, Szu-Ju Li, and Yao-Tsung Tsai, “Device-partition Method Using Equivalent-Circuit Model in Three-Dimensional Device Simulation,” Solid-State Electronics, Vol. 50, pp. 1206-1211, 2006. (SCI, NSC 94-2516-S-008-002)

  16. Chia-Cherng Chang, Szu-Ju Li, and Yao-Tsung Tsai, “An Equivalent-Circuit Modelling on Vertical and Horizontal Integrations for MOS Flat-Band Voltage Simulation,” International Journal of Numerical Modelling-Electronic Networks Devices and Fields, Vol. 19, pp.289–300, 2006. (SCI, NSC 93-2516-S-008-001)

  17. Szu-Ju Li, Chia-Cherng Chang, and Yao-Tsung Tsai, “Simulation of Si N-MOS Inversion Layer with Schrodinger-Poisson Equivalent Circuit Model,” International Journal of Numerical Modelling-Electronic Networks Devices and Fields, Vol. 19, pp.229–238, 2006. (SCI, NSC 93-2516-S-008-001)

  18. Chia-Cherng Chang, Szu-Ju Li, and Yao-Tsung Tsai, “Device-Partition Method Using Equivalent Circuit Model in Two-Dimensional Device Simulation,” International Journal of Numerical Modelling-Electronic Networks Devices and Fields, Vol. 18, No. 3, pp. 203-219, 2005. (SCI, NSC 92-2516-S-008-001)

  19. Jing-Fu Dai, Chia-Cherng Chang, Szu-Ju Li, and Yao-Tsung Tsai, “Further Improvements in Equivalent-Circuit Model with Levelized Incomplete LU Factorization for Mixed-Level Semiconductor Device and Circuit Simulation,” Solid-State Electronics, Vol. 48, pp. 1181-1188, 2004. (SCI, NSC 91-2516-S-008-002)

  20. Jing-Fu Dai, Chia-Cherng Chang, J.-W. Lee, Szu-Ju Li, and Yao-Tsung Tsai, “Simplified Equivalent-Circuit Modeling for Decoupled and Partial Decoupled Methods in Semiconductor Device Simulation,” International Journal of Numerical Modelling-Electronic Networks Devices and Fields, Vol. 17, pp. 421-432, 2004.( SCI, NSC 91-2516-S-008-002)

  21. Chia-Cherng Chang, Jing-Fu Dai, and Yao-Tsung Tsai, “Verification of 1D BJT Numerical Simulation and Its Application to Mixed-Level Device and Circuit Simulation,” International Journal of Numerical Modelling-Electronic Networks Devices and Fields, Vol. 16, pp. 81-94, 2003. (SCI, NSC 90-2516-S-008-001)

  22. Chia-Cherng Chang, Jing-Fu Dai, Y.-M. Sun, and Yao-Tsung Tsai, “Levelized incomplete LU factorization and its application to quasi-static MOSFET C-V simulation,” Journal of the Chinese Institute of Engineers, Vol. 10, No. 2, pp. 117-123, May, 2003. (SCI, NSC 90-2516-S-008-001)

  23. Yao-Tsung Tsai, Jing-Fu Dai, and M.-K. Tsai, “An Improved Levelized Incomplete LU Method and Its Application to 2D Semiconductor Device Simulation,” Journal of the Chinese Institute of Engineers, Vol. 24, No. 3, pp. 389-396, 2001. (SCI, NSC 89-2213-E-008-043)

  24. Yao-Tsung Tsai, C.-Y. Lee, and M.-K. Tsai, “Levelized Incomplete LU Method and Its Application to Semiconductor Device Simulation,” Solid-State Electronics Vol. 44, pp. 1069-1075, 2000. (SCI, NSC 88-2213-E-008-012)

  25. Yao-Tsung Tsai and W.-H. Yang, “Transient Simulation of A-Si TFT/LCD Pixel Using Table-Modeling Techniques,” Journal of the Chinese Institute of Engineers, Vol. 22, No. 1, pp. 87-92, January 1999. (SCI, NCHC-86-03-009)

  26. Yao-Tsung Tsai and C.-L. Teng, “Two-Dimensional Mixed-Level Device and Circuit Simulation Using HSPICE,” Proceedings of the National Science Council, Republic of China, Vol. 22, No. 2, pp. 290-296, March 1998. (NSC 86-2215-E-008-016)

  27. Yao-Tsung Tsai and T.-C. Ke, “Electrode Separation Method to the Boundary Condition for A-Si TFT Mixed-Level Simulation,” International Journal of Numerical Modelling-Electronic Networks Devices and Fields, Vol. 11, pp. 123-130, 1998. (SCI, NSC 86-2215-E-008-016)

  28. Yao-Tsung Tsai and L.-C. Huang, “Simulation of Amorphous Silicon Thin-Film Transistor Including Adapted Gummel Method,” International Journal of Numerical Modelling-Electronic Networks Devices and Fields, Vol. 10, No. 1, pp. 3-12, 1997. (SCI, NSC 84-2215-E-008-015)

  29. Yao-Tsung Tsai, J.-M. Shyu and B.-A. Yuan, “A Sparse Matrix Solver for Circuit Simulation,” Journal of The Chinese Institute of Engineers, Vol. 3, No. 3, pp. 269-274, Aug. 1996. (EI, NSC 84-2215-E-008-015)

  30. Yao-Tsung Tsai, B.-A. Yuan, and J.-M. Shyu, “An Algorithm to Extract Circuit and Physical Model of A-Si TFT,” Proceedings of the National Science Council, Republic of China, Vol. 20, No. 3, pp. 294-303, May 1996. (NSC 84-0404-E-008-015)

  31. Yao-Tsung Tsai, Y.-L. Yuan, and K.-D. Hong, “A Circuit Simulator Including User-Defined Devices,” Proceedings of the National Science Council, Republic of China, Vol. 18, No. 6, pp. 603-613, Nov. 1994. (NSC 82-0404-E-008-076)

  32. Yao-Tsung Tsai, K.-D. Hong, and Y.-L. Yuan, “An Efficient Analytical Model for Calculating Trapped Charge in Amorphous Silicon,” IEEE Trans. Computer-Aided Design, Vol. 13, No. 6, pp. 725-728, Jun. 1994. (SCI, NSC 82-0404-E-008-076)

  33. Yao-Tsung Tsai and T.-A. Grotjohn, “Small-Signal Analysis of MESFET's including the Energy Conservation Equation,” IEEE Trans. Computer-Aided Design, Vol. 10, No. 12, pp. 1530-1533, Dec. 1991. (SCI)

  34. Yao-Tsung Tsai and T.-A. Grotjohn, “Source and Drain Resistance Studies of Short-Channel MESFET Using Two-Dimensional Device Simulators,” IEEE Trans. Electron Devices, Vol. ED-37, pp. 775-78, Mar. 1990. (SCI)

  35. C.-Y. Wu, H.-D. Sheng, and Yao-Tsung Tsai, “The Lambda Bipolar Photo-Transistor -- Analysis and Applications,” IEEE Journal of Solid-State Circuits, Vol. SC-18, pp. 1227-1234, Dec. 1985. (SCI)

(B) Conference Papers:

  1. Feng-Tso Chien, Chien-Liang Chan, Chin-Mu Fang, Chien-Nan Liao, and Yao-Tsung Tsai, “Low Gate Leakage Current HEMTs by a New Airbridge Gate and a Liquid Oxidization Surface,” Asia-pacific workshop on fundamentals and applications of advanced semiconductor devices, AWAD, pp. 283-286, 2007, Korea.

  2. Feng-Tso Chien, Chien-Nan Liao, and Yao-Tsung Tsai, “A Novel High Channel Density Trench Power MOSFETs Design by Asymmetric Wing-Cell Structure,” 12th IEEE European Conference on Power Electronics and Applications, pp. 1-7, 2007, Denmark.

  3. Chien-Nan Liao, Feng-Tso Chien, and Yao-Tsung Tsai, “Potential and Electric Field Distribution Analysis of Field Limiting Ring and Field Plate by Device Simulator,” 7th IEEE International Conference on Power Electronics and Drive Systems, PEDS, pp. 451-455, 2007, Thailand.

  4. Chien-Nan Liao, Feng-Tso Chien, and Yao-Tsung Tsai, “Low Switching Loss Power MOSFET with Dual Gate Structure,” Asia-pacific workshop on fundamentals and applications of advanced semiconductor devices, AWAD, pp. 308-311, 2007, Korea.

  5. Chi-Hon Ho, Szu-Ju Li, Ho-Chieh Wu, and Yao-Tsung Tsai, “A special capacitance model for numerical metal-gate simulation,” 2006 IEDMS, PD088, Tainan, Dec. 2006.

  6. Szu-Ju Li, Chi-Hon Ho, and Yao-Tsung Tsai, “Kronig-Penney Model Simulation with Equivalent Circuit Method,” 2006 IEDMS, PA006, Tainan, Dec. 2006.

  7. Szu-Ju Li, Chi-Hon Ho, and Yao-Tsung Tsai, “An Efficient Simulation Technique for 1D Semiconductor Device in Frequency Domain, 2006 IEDMS, PA061, Tainan, Dec. 2006.

  8. Chia-Cherng Chang, Szu-Ju Li, and Yao-Tsung Tsai, “Two-dimensional mixed-level device and circuit simulation using a simple band matrix solver,” 2005 EDMS, AO12, Kaohsiung, Nov. 2005.

  9. Chia-Cherng Chang, Szu-Ju Li, and Yao-Tsung Tsai, “Device-partition method using equivalent-circuit model in three-dimensional device simulation,” 2005 EDMS, AO12, Kaohsiung, Nov. 2005.

  10. Szu-Ju Li, Chia-Cherng Chang, and Yao-Tsung Tsai, “Si n-MOS Simulation in inversion layer with Schrodinger-Poisson equivalent circuit model,” 2005 EDMS, AO12, Kaohsiung, Nov. 2005.

  11. Szu-Ju Li, Chia-Cherng Chang, and Yao-Tsung Tsai, “Time-domain Numerical Simulation for Understanding Scattering Parameters,” 2005 EDMS, AO12, Kaohsiung, Nov. 2005.

  12. Jing-Fu Dai, Chia-Cherng Chang, Szu-Ju Li, and Yao-Tsung Tsai, “Further improvements in equivalent-circuit model with levelized incomplete LU factorization for mixed-level semiconductor device and circuit simulation,” 2003 EDMS, pp. 54-57, Keelung, Dec. 2003.

  13. Szu-Ju Li, Jing-Fu Dai, Chia-Cherng Chang, and Yao-Tsung Tsai, “Quantum effects in Si n-MOS inversion layer with simple numerical method,” 2003 EDMS, pp. 662-665, Keelung, Dec. 2003.

  14. Zhi-Hao Lin, Szu-Ju Li, and Yao-Tsung Tsai, “An efficient analytical model for carrier calculation including Fermi-Dirac integration and its applications to device simulation,” 2003 EDMS, pp. 787-790, Keelung, Dec. 2003.

  15. Chia-Cherng Chang, Chau-Hsin Huang, Jing-Fu Fai, Szu-Ju Li, and Yao-Tsung Tsai, “Device-partition method in two dimensional device simulation,” 2003 ICICS, pp. 56, Kaohsiung ,Dec. 2003.

  16. Jing-Fu Dai, Chia-Cherng Chang, Szu-Ju Li, and Yao-Tsung Tsai, “A more efficient equivalent-circuit model for levelized incomplete LU factorization in semiconductor device simulation,” 2002 IEDMS, Taipei, Dec. 2002.

  17. Szu-Ju Li, Jing-Fu Dai, Chia-Cherng Chang, and Yao-Tsung Tsai, “An equivalent circuit of impact-ionization and it’s applications on semiconductor devices,” 2002 IEDMS, Taipei, Dec. 2002.

  18. Chia-Cherng Chang, Chau-Hsin Huang, Jing-Fu Fai, Szu-Ju Li, and Yao-Tsung Tsai, “3-D numerical device simulation including equivalent-circuit model,” 2002 IEDMS, Taipei, Dec. 2002.

  19. Jing-Fu Dai, Chia-Cherng Chang, and Yao-Tsung Tsai, “A simplified equivalent-circuit model for decoupled method in semiconductor-device simulation,” 2002 VLSI/CAD, Taiwan.

  20. 蔡曜聰, 蔡木凱, 王少甫, 翁贊博, “利用階層化不完全法建構之稀疏矩陣解法器及 其在半導体元件模擬上之應用,”EDMS’99, Taoyuan, Nov. 1999.

  21. Yao-Tsung Tsai, Zu-Chang Liu, and Chun-Yi Lee, “Comparison of two potential variables in mixed-level device and circuit simulation,” IEDMS’98, Tainan, Dec. 1998.

  22. Yao-Tsung Tsai and T.-C. Ke, “Network analysis approach to numerical a-Si TFT simulation,” 1997 IEEE Hong Kong Electron Devices Meeting, pp. 42-45, Hong Kong, August 30, 1997.

  23. Yao-Tsung Tsai, C.-L. Teng, and T.-C. Ke, “Transient numerical simulation of device and circuit using HSPICE,” High-Performance Computing, HPC Asia'97 Conference and Exhibition, Seoul, Korea, April 28-May 2, 1997.

  24. Yao-Tsung Tsai, C.-L. Teng, and T.-C. Ke, “A circuit model for transient device simulation using a circuit simulator,” IASTED International Conference on Modelling and Simulation, Pittsburgh, Pennsylvania, USA, pp. 296-298, May 14-17, 1997.

  25. Yao-Tsung Tsai, L.-C. Huang, and S.-T. Yang, “Computer simulation and analysis of a-Si TFT/LCD pixels,” IEDMS'96, Hsinchu, Taiwan, pp. D1-4-p.271--D1-4-p.274, Dec. 1996.

  26. C.-T. Ou and Yao-Tsung Tsai, “A mixed-mode Monte Carlo simulation,” 1996 Semiconductor Technology CAD Workshop and Exhibition, Hsinchu, Taiwan, May 1996.

  27. J.-H. Lin and Yao-Tsung Tsai, “AC analysis of semiconductor devices using Monte Carlo simulation,” 1996 Semiconductor Technology CAD Workshop and Exhibition, Hsinchu, Taiwan, May 1996.

  28. Yao-Tsung Tsai, B.-A. Yuan, and J.-M. Shyu, “Parameter extraction of amorphous-silicon thin-film transistors,” High-Performance Computing, HPC Asia'95 Conference and Exhibition, Taipei, Taiwan, 1995.J.-M. Shyu, B.-A.

  29. B.-A. Yuan and Yao-Tsung Tsai, “A simulation tool for circuit design of amorphous-silicon thin-film transistor,” EDMS'95, Taiwan, pp. 471-476, 1995.

  30. Yao-Tsung Tsai, K.-D. Hong, and Y.-L. Yuan, “A simple adapted Gummel method for amorphous silicon device simulation,” IEDMS'94, Taiwan, pp. 11.38.152-11.38.155, 1994.

  31. Y.-L. Yuan, K.-D. Hong, and Yao-Tsung Tsai, “A circuit simulator including amorphous silicon thin-film transistor,” EDMS'93, Taiwan, pp. 136-139, 1993.

  32. Yao-Tsung Tsai, K.-D. Hong, and Y.-L. Yuan, “An Efficient Trapped-Charge Calculation in Amorphous Silicon for Device Simulation,” IEEE 1993 Symposium on Semiconductor Modeling and Simulation, Taipei, Taiwan, ROC, March 6-7, pp. 75-76, 1993.

  33. Yao-Tsung Tsai, “A circuit simulator including user-defined devices,” Intern. multiconference “signals, data, systems, Calcutta (India), Dec. 7-9, 1992.

  34. C.-C. Su, S.-J. Jou, K.-T. Chen, Yao-Tsung Tsai, C.-L. Tseng, and C.-K. Wang, “The NCU CAD system -- A Practical Approach,” SINO-GERMAN VLSI/CAD workshop, Tainan, Taiwan, R.O.C., pp. 12-18., 1991.

(C) Other Publications:

  1. Yao-Tsung Tsai, “Development of template circuit simulator and its applications in circuit and 2D device analysis,” Research Report, NSC 93-2516-S-008-001-, 2005.

  2. Yao-Tsung Tsai, “A study on quantum effects of nano devices for research and teaching,” Research Report, NSC 92-2516-S-008-001-, 2004.

  3. Yao-Tsung Tsai, “The tool development of AC characteristic analysis in two-dimensional semiconductor devices,” Research Report, NSC 92-2516-S-008-002-, 2004.

  4. Yao-Tsung Tsai, “Comparison between coupled and decoupled equivalent circuit models in 2D MOSFET simulation using L-ILU solver,” Research Report, NSC 91-2516-S-008-002-, 2003.

  5. Yao-Tsung Tsai, “3-Dimensional silicon-on-insulator MOSFET simulation,” Research Report, NSC 91-2516-S-008-001-, 2003.

  6. Yao-Tsung Tsai, “Teaching semiconductor device physics with a pc-based numerical sparse matrix solver, Research Report, NSC 90-2516-S-008-001, 2002.

  7. Yao-Tsung Tsai, “元件的直流交流和暫態模擬之數值量測並 包含改善後的階層化全LU分解法,” 研究報告, NSC 89-2213-E-008-043, 2001.

  8. Yao-Tsung Tsai, “利用階層化不完全LU 法建構之稀疏矩陣解法器及其在半導体件模擬上之應用 ,” 研究報告, NSC 88-2213-E-008-012, 2000.

  9. Yao-Tsung Tsai, “Two-dimensional numerical device and mixed-level simulation using a direct-method circuit simulator,” Research Report, NSC 87-2215-E-008-024, 1999.

  10. Yao-Tsung Tsai, “A study on submicron MOS device modeling,” Research Report, NSC 86-2215-E-008-016, 1998.

  11. Yao-Tsung Tsai, “Transient simulation of a-Si TFT/LCD pixel using table-modeling techniques,” Research Report, NCHC-86-03-009, 1998.

  12. J.-W. Hong and Yao-Tsung Tsai, “Simulation and fabrication of a-Si TFT/LCD pixels,” Research Report, CHUNGHWA PICTURE TUBES, LTD, 1997.

  13. Yao-Tsung Tsai, “A mixed-mode Monte Carlo simulation,” Research Report, NSC 85-2215-E-008-023, 1997.

  14. Yao-Tsung Tsai, “Low-voltage low-power device and circuit characterization,” Research Report, NSC 85-2221-E-008-022, 1997.

  15. Yao-Tsung Tsai, “AC characterization of semiconductor devices using the Monte-Carlo method,” Research Report, NSC 84-2215-E008-001, 1996.

  16. Yao-Tsung Tsai, “Performance improvement of circuit simulation,” Research Report, NSC 83-0404-E008-015 and NSC 84-2215-E008-015, 1996.

  17. Yao-Tsung Tsai, “Circuit design techniques for scaled CMOS technology,” Research Report, NSC 84-2215-E008-015, 1996.

  18. Yao-Tsung Tsai, “Computer-aided design of amorphous silicon thin-film transistors,” Research Report, NSC 83-0404-E008-003, 1995.

  19. Yao-Tsung Tsai, “A circuit simulator including user-defined devices,” Research Report, NSC 82-0404-E008-076, 1994.

  20. Yao-Tsung Tsai, J.-W. Hong and J.-I. Chyi, “Characteristics and analysis of pixel for a-Si:H TFT LCD,” Research Report, NSC 81-0417-E008-06, 1993.

  21. Yao-Tsung Tsai, “Behavioral modeling language for analog circuit design,” Research Report, NSC 81-0404-E008-102, 1993.

  22. Yao-Tsung Tsai, “AC Simulation of Field Effect Transistors with a Hydrodynamic Transport Model,” Ph. D. thesis in Electrical Eng., Michigan State University, U.S.A., 1990.

  23. Yao-Tsung Tsai, “The Lambda Bipolar Photo-Transistor -- Analysis and Applications,” M. S. thesis in Electronic Eng., National Chiao Tung University, Taiwan, R.O.C., 1984.

(D) 學生論文題目:

  1. 廖健男, “Low Power Loss Power Vertical Double-diffused MOSFET,” Ph. D. Thesis, National Central University, Taiwan, 2010.

  2. 何志宏, “Branch-cut Method for the SOI MOSFETs Simulation and the Characteristics Analysis of Back Gate Bias Effect for the SOI Power Devices,” Ph. D. Thesis, National Central University, Taiwan, 2009.

  3. 李思儒, “Semiconductor Device Simulation with Equivalent Circuit Model including Quantum Effect,” Ph. D. Thesis, National Central University, Taiwan, 2007.

  4. 張家誠, “Improvement of 2-D and 3-D Semiconductor Device Simulation Using Equivalent-circuit Model,” Ph. D. Thesis, National Central University, Taiwan, 2006.

  5. 戴菁甫, “Development of 2-D and 3-D Numerical Device Simulator including an Improved L-ILU Solver and the Circuit Representation of PDM,” Ph. D. Thesis, National Central University, Taiwan, 2004.

  6. 王傑龍, “Theoretical Analysis and Simulation of Cylindrical PN Diode for Breakdown Characteristics,” M. S. Thesis, National Central University, Taiwan, 2010.

  7. 左裕昇, “Analysis and Simulation of Curved PN Junction in Cylindrical Coordinates,” M. S. Thesis, National Central University, Taiwan, 2010.

  8. 洪嘉良, “Analysis and Simulation of 2-D Semiconductor Device by Linear Components,” M. S. Thesis, National Central University, Taiwan, 2010.

  9. 林彥智, “Analysis and Simulation of Nonlinear MOSFET Circuits by Linear Components,” M. S. Thesis, National Central University, Taiwan, 2010.

  10. 吳浩銓, “Analysis and Applications of Bezier Curve in Device and Circuit Simulation,” M. S. Thesis, National Central University, Taiwan, 2010.

  11. 張惟傑, “Analyzing Any Nonlinear Device and Circuit by Basic Linear Components,” M. S. Thesis, National Central University, Taiwan, 2009.

  12. 王君正, “Curvature Effect and Back Gate Bias Effect on Semiconductor Device Breakdown Simulation,” M. S. Thesis, National Central University, Taiwan, 2009.

  13. 蔡志維, “Suraface Recombination Current and Non-Bernoulli Equation for 2-D Semiconductor Device Simulation,” M. S. Thesis, National Central University, Taiwan, 2009.

  14. 應子翔, “Power and Temperature Distribution by 2-D Semiconductor Device Simulation,” M. S. Thesis, National Central University, Taiwan, 2009.

  15. 黃緯浩, “Heterojunction Modeling and its application in 2D HBT simulation,” M. S. Thesis, National Central University, Taiwan, 2008.

  16. 彭俊益, “Current Characteristic and Electric-field Analysis in 2-D SOI Semiconductor Device Simulation,” M. S. Thesis, National Central University, Taiwan, 2008.

  17. 沈永吉, “Integration of Band solver and LILU Solver for 2D Semiconductor Device Simulation,” M. S. Thesis, National Central University, Taiwan, 2008.

  18. 張嘉顯, “Development of 1-D and 2-D Schottky Diode Device Simulation Using Equivalent-circuit Model,” M. S. Thesis, National Central University, Taiwan, 2008.

  19. 洪國源(碩士在職專班), “Integration of Band Solver and BILU Solver for 3-D Device Simulation,” M. S. Thesis, National Central University, Taiwan, 2008.

  20. 黃煒龍(碩士在職專班), “Integration of Band Solver and LILU Solver for 3-D Device Simulation,” M. S. Thesis, National Central University, Taiwan, 2008.

  21. 王郁誠, “Frequency-domain Numerical Simulation for Finding Scattering Parameters,” M. S. Thesis, National Central University, Taiwan, 2007.

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