Introduction to Digital System, Spring 2004
ANNOUNCEMENT
- (May 27) The final exam is hold on Jun. 15 (Tue.) 13:00-15:00 at E1-121.
- (Mar. 30) The midterm is scheduled at Apr. 15 (Thu.) with only ONE hour.
- (Mar. 24) The VCR
of this course is available now.
- (Feb. 26) The courses at next week (3/1~3/5) are cancelled.
INSTRUCTOR: Chien-Nan Liu
TEACHING ASSISTANTS
COURSE SCHEDULE
- Binary Systems
- Boolean Algebra and Logic Gates
- Gate-Level Minimization
- Combinational Logic
- Synchronous Sequential Logic
- Registers and Counters
- Memory and Programmable Logic
LECTURE NOTES
HOMEWORKS
- Homework 1:
1-8, 1-9, 1-20 (Due: Mar. 9, 2004)
- Homework 2: 1-29, 1-32 (Due: Mar. 18, 2004)
- Homework 3: 2-2, 2-6, 2-15 (Due: Mar. 25, 2004)
- Homework 4: 2-17, 2-18, 2-19 (Due: Mar. 31, 2004)
- Homework 5: 3-10, 3-13, 3-15 (Due: Apr. 8, 2004)
- Homework 6: 3-17, 3-19(a), 3-22, 3-24 (Due: Apr. 15, 2004)
- Homework 7: 4-1(a)(b), 4-5, 4-13, 4-20 (Due: Apr. 29, 2004)
- Homework 8: 4-27, 4-29, 4-31, 4-32 (Due: May 6, 2004)
- Homework 9: 4-29 (use Altera simulation), 5-1 (Due: May 13, 2004)
- Homework 10: 5-7, 5-10, 5-11 (compared with Altera simulation)
(Due: May 20, 2004)
- Homework 11: 5-12, 5-19(b), 5-16 (verified by Altera simulation)
(Due: May 27, 2004)
- Homework 12: 6-8, 6-12, 6-22, 6-27 (Due: Jun. 3, 2004)
PROJECTS
For any questions, send e-mails to
jimmy@ee.ncu.edu.tw
Last modified: May 27, 2004