Design and Verification Methodology for SoC, Fall 2017
ANNOUNCEMENT
- We will have the final exam at 1/11 (Thu), starting from 1000.
- We will have a midterm at 10/26 (Thu), starting from 1000.
- In this semester, the class will start from 9:30.
INSTRUCTOR: Chien-Nan Liu
TEACHING ASSISTANT
COURSE SCHEDULE
- Introduction to SoC design and verification (1 week)
- Reusable design methodology (1 week)
- --< Mini report >--
- System specification and modeling (2 weeks)
- Introduction to system modeling (3hrs)
- SystemC overview (3hrs)
- Verification methodology for SoC (1 week)
- Coverage-driven functional verification methodology (3hrs)
- --< Coverage analysis exercise using VCS >--
- Static verification techniques (2 weeks)
- HDL lint checking (2hrs)
- Formal verification (2hrs)
- Static timing analysis (STA) (2hrs)
- Low-power design methodology (2 weeks)
- Power estimation overview (3hrs)
- --< Power estimation exercise >--
- System-level low-power design techniques (3hrs)
- Analog/mixed-signal system simulation (3 weeks)
- Introduction to AMS behavior modeling (3hrs)
- Verilog-A overview (3hrs)
- --< Verilog-A exercise >--
- Case study of AMS behavior modeling (3hrs)
- Automatic analog design methodology (2 weeks)
- Introduction to analog design automation (3hrs)
- Automated robust design optimization for analog circuits (3hrs)
LECTURE NOTES
- Syllabus (Sep. 6, 2017)
- Please go to NCU LMS system to download the slides.
HOMEWORKS AND PROJECTS
- Mini Report (Due: Oct. 19, 2017)
- Coverage analysis exercise using VCS
- Power estimation exercise using PTPX
- Verilog-A exercise using Virtuoso
For any questions, send e-mails to
jimmy@ee.ncu.edu.tw
Last modified: Jan. 8, 2018