EE 6083 Semiconductor Memory Testing

Jin-Fu Li

jfli@ee.ncu.edu.tw

Spring 2008

Reference Books:

1. Cheng-Wen Wu, "Specific Semiconductor Memory Testing", Lecture Notes of SOC Consortium, MOE.
2. Jin-Fu Li, "Yield-Enhancement Techniques for Embedded Memories", Lecture Notes of SOC Consortium, MOE.
3. Wang, Wu, and Wen,"VLSI Test Principles and Architectures", Elsevier, 2006.
4. ve de Goor,"Testing Semiconductor Memories: Theory and Practice", John Wiley & Sons, Chichester, England, 1991.

Transparencies

• Semiconductor Memory Testing-Syllabus
• Introduction-Chapter 1 (Part 1) Chapter 1 (Part 2)
• RAM Functional Faults-Chapter 2
• RAM Testing-Chapter 3
• Memory Built-In Self-Test-Chapter 4
• Content Addressable Memory TestingChapter 5
• Memory DiagnosisChapter 6
• Memory Testing Introduction (Manager M.-W. Wang, Verigy Ltd. Taiwan Branch)Memory_Test_Introduction
• Memory Built-In Self-RepairChapter 7
• Transparent BIST for RAMsChapter 8

Homeworks

• Homework #2-HW2 (due, Mon. May 19)

Grading:

1. Homework 20%
2. Midterm 50%
3. Final Project 30%

Midterm:10:00-12:00, Tues., April 29, E1-120

Project Proposal:May 13

Project Presentation:June 15 and 16

Project Report:By 17:00, June 20