EE 4029 VLSI Design and Implementation

Jin-Fu Li

jfli@ee.ncu.edu.tw

Fall 2012

Transparencies

• VLSI Design and Implementation (Cell-Based Design) Introduction
• Verilog Coding Style Topic 1
• Lab 1Lab 1
• Design Compiler Topic 2
• Lab 2Lab 2
• SOC Encounter Topic 3
• Lab 2Lab 3

Homeworks

Statistics

Grading:

1. Three Labs 30%
2. Exam 20%

• Overdue homework is not accepted.
• The course takes attendance unpredictably.