EE 8086 SOC Testing

Jin-Fu Li

jfli@ee.ncu.edu.tw

Spring 2009

Text Books

1. L.-T. Wang, C. E. Stroud, and N. A. Tuba,"System On Chip Test Architectures", Elsevier, 2008.

Reference Books

1. L.-T. Wang, C.-W. Wu, and X. Wen,"VLSI Test Principles and Architectures", Elsevier, 2006.
2. Bushnell and Agrawal,"Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits",Kluwer Academic Pubishers, 2000.

Transparencies

• SOC Testing-Syllabus
• Introduction-Chapter 1
• Basics of VLSI Testing(1)-Chapter 2
• Basics of VLSI Testing (2)-Chapter 3
• Digital Test Architectures-Chapter 4
• System/Network-on-Chip Test Architectures-Chapter 5
• System-in-Package Testing-Chapter 6
• RAM Testing-Chapter 7
• Yeild and Reliability-Enhancement Techniques for RAMs-Chapter 8

Homeworks

Grading:

1. Homework 30%
2. Midterm 40%
3. Final 30%

Midterm:10:00-12:00, Mon., May 4, E1-105

Final Project Presentation:10:00-12:00, June 15, 16, and 21, E1-105

Final Project Report:By 17:00, June 26, E1-402