Digital System Design, Spring 2006
ANNOUNCEMENT
- The demo time of final project has been moved to Jun. 26 (Monday).
INSTRUCTOR: Chien-Nan Liu
TEACHING ASSISTANT
COURSE SCHEDULE
- Introduction to HDL-based design methodology (1 week)
- Asynchronous sequential logic (2 weeks)
- Language fundamentals -- Verilog HDL (2 weeks)
- Verilog simulation (1 week)
- FPGA synthesis using Verilog (1 week)
- Modeling combinational logic circuits (1 week)
- Modeling sequential elements (1 week)
- Modeling finite state machines (1 week)
- Modeling digital systems (1 week)
- Introduction to HDL synthesis (1 week)
- Timing issues in digital designs (1 week)
- Final Project (2 weeks)
LECTURE NOTES
- Syllabus (Feb. 1, 2006)
- lecture 1 (Introduction, Feb. 1, 2006)
- lecture 2 (Asynchronous Circuits, Feb. 1, 2006)
- lecture 3 (Verilog Overview, Feb. 1, 2006)
- lecture 4 (Model Comb. Circuits, Feb. 1, 2006)
- lecture 5 (Model Seq. Circuits, Feb. 1, 2006)
- lecture 6 (Model FSM, Feb. 1, 2006)
- lecture 7 (Model Systems, Feb. 1, 2006)
- lecture 8 (Synthesis Overview, Feb. 1, 2006)
- lecture 9 (Timing Issues, Feb. 1, 2006)
- Installation Guide of ISE and ModelSim
(Apr. 7, 2006)
HOMEWORKS
Homework 1: 9-4, 9-11 (Due: Mar. 23, 2006)
Homework 2: 9-14, 9-15(a), 9-18(table a only), 9-21
(Due: Apr. 6, 2006)
Homework 3 (Due: Apr. 13, 2006)
Homework 4 (Due: Apr. 20, 2006)
Homework 5 (Due: Apr. 27, 2006)
Homework 6 (Due: May 4, 2006)
Homework 7 (Due: May 11, 2006)
Homework 8 (Due: May 18, 2006)
Homework 9 (Due: Jun. 1, 2006)
FINAL PROJECTS
Project #1 (Due: Jun. 26, 2006)
Project #2 (Due: Jun. 26, 2006)
Project #3 (Due: Jun. 26, 2006)
Project #4 (Due: Jun. 26, 2006)
Please send a mail to corresponding TAs to register the project
of your group before May 9.
Note that the maximum number of groups for a problem is set to
10 only.
If more than 10 groups are going to solve the same problem,
we will take only the first 10 groups who register this problem.
Therefore, please make your decision as soon as possible.
We will arrange a demo time on Jun. 26 (Monday).
Please have your design and report ready before the demo time.
For any questions, send e-mails to
jimmy@ee.ncu.edu.tw
Last modified: Jun. 7, 2006